MT48H8M16LFB4-10 Micron Technology Inc, MT48H8M16LFB4-10 Datasheet - Page 43

• Manufacturer Part Number: MT48H8M16LFB4-10
• Description: IC SDRAM 128MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-10

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every 2 clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
22. V
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured for 1.8V at 0.9V with equivalent load:
1.4V. f = 1 MHz.
with minimum cycle time and the outputs open.
operation over the full temperature range (-25°C ≤ T
40°C ≤ T
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sit between V
t
a reference to V
High-Z.
point. If the input transition time is longer than
enced at V
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
cannot be greater than one third of the cycle rate. V
a pulse width ≤ 3ns.
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
IH
specifications are tested after the device is properly initialized.
overshoot: V
is dependent on output loading and cycle rates. Specified values are obtained
DD
A
Q
current will increase or decrease proportionally according to the amount of
t
≤ +85°C for IT parts) is ensured.
CK = 8ns for -8 and
IL
(MAX) and V
IH
and V
DD
OH
IH
tests have V
(MAX) = V
or V
IL
30pF
IH
(or between V
OL
IH
or V
. The last valid data element will meet
t
43
SS
SS
T = 1ns.
(MIN) and no longer at the V
t
.
t
WR.
and V
CKS; clock(s) specified as a reference only at minimum
t
t
IL
DD
DD
CK = 9.6ns for -10.
WR plus
IL
levels.
, V
Q + 2V for a pulse width ≤ 3ns, and the pulse width
and V
DD
SS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q must be at same potential.) The two AUTO
IL
Q = +1.8V; T
IH
t
and V
RP; clock(s) specified as a reference only at
, with timing referenced to V
IH
) in a monotonic manner.
128Mb: x16 Mobile SDRAM
t
A
T (MAX), then the timing is refer-
IL
= 25°C; ball under test biased at
undershoot: V
A
≤ +85°C for standard parts; -
IH
DD
/2 crossover point.
©2003 Micron Technology, Inc. All rights reserved.
and V
t
REF refresh require-
DD
t
IL
OH before going
IH
Q must be pow-
(MIN) = -2V for
/2 = crossover
Notes