MT48H8M16LFB4-10 Micron Technology Inc, MT48H8M16LFB4-10 Datasheet
MT48H8M16LFB4-10
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MT48H8M16LFB4-10 Summary of contents
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Synchronous DRAM MT48H8M16LF - 2 Meg banks Features • Temperature compensated self refresh (TCSR) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 54-Ball FBGA Assignment (Top View ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access opera- tion. The 128Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, deep power-down mode. All inputs and outputs are LVTTL-compatible. ...
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... BA0, BA1 REGISTER 2 8 PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN BANK1 12 BANK0 ROW- 12 ADDRESS ROW- BANK0 MUX ADDRESS MEMORY 4096 LATCH ARRAY & (4,096 x 512 x 16) DECODER SENSE AMPLIFIERS 4096 I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS ...
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... A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command ...
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Functional Description In general, the 128Mb SDRAMs (2 Meg banks) are quad-bank DRAMs that oper- ate at 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). ...
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Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4, "Mode Register Definition," on page 11. The burst length determines the maximum number of column locations that ...
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Table 4: Burst Definition Burst Length Full Page (y) Notes: 1. For full-page accesses 512. 2. For A1–A8 select the block-of-two burst; A0 selects the starting column within the block. 3. For ...
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Figure 4: Mode Register Definition ** BA1, BA0 = “0, 0” to prevent Extended Mode Register. Note: The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page ...
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For example, assuming that the clock cycle time is such that all relevant access times are met read command is registered at T0 and the latency is ...
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... Partial Array Self Refresh For further power savings during SELF REFRESH, the partial array self refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed dur- ing SELF REFRESH. The refresh options are all banks (banks and 3); two banks (banks 0 and 1) ...
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This drive option is not recommended for loads under 15pF. Quarter drive strength is intended for lighter loads or point-to-point systems. Figure 6: Extended Mode Register Diagram BA1 E13 13 1 ...
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Commands Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following "Operation" on page 18; these tables provide current state/next state information. Table 6: ...
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... Input data appearing on the DQ is written to the memory array subject to the DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data will be written to mem- ory ...
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BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued ...
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... Deep Power-Down The operating mode deep power-down achieves maximum power reduction by elimi- nating the power of the whole memory array of the device. Array data will not be retained once the device enters deep power-down mode. This mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# held HIGH at the rising edge of the clock, while CKE is LOW ...
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Figure 7: Activating a Specific Row in a Specific Bank Register RAS# CAS# A0–A10, A11 BA0, BA1 t Figure 8: Meeting RCD (MIN) When 2 < CLK COMMAND READs READ bursts are initiated with a READ command, as shown in ...
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The new READ com- mand should be issued x cycles before the clock edge at which the last desired data ele- ment is valid, where x equals the ...
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Figure 10: Consecutive READ Bursts CLK COMMAND ADDRESS CLK COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev READ NOP NOP NOP ...
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Figure 11: Random READ Accesses CLK COMMAND ADDRESS CLK COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. The DQM input is used to avoid I/O contention, as shown in Figure 12 and Figure 13 ...
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PRECHARGE command, a subsequent command to the same bank cannot be issued t until the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE com- mand issued at the optimum time (as described ...
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Figure 14: READ-To-PRECHARGE CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ Note: DQM is LOW. Figure 15: Terminating a READ Burst CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ Note: DQM is LOW. PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E ...
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Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, pro- vided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles ...
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WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a different bank. Figure 17: WRITE Burst CLK COMMAND ADDRESS Note: ...
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In the case of a fixed-length burst being executed to completion, a PRECHARGE com- mand issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvan- ...
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Figure 21: WRITE-To-PRECHARGE CLK 15ns DQM COMMAND ADDRESS < 15ns DQM COMMAND ADDRESS DQ Note: DQM could remain LOW in this example if the WRITE burst is a fixed ...
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Figure 22: Power-Down CLK CKE COMMAND Figure 23: Terminating a WRITE Burst COMMAND ADDRESS Note: DQMs are LOW. PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev CKS ( ( ) ...
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... Deep Power-Down Deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. Data on the memory array will not be retained once deep power-down mode is executed. Deep power-down mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW ...
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BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column ...
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Concurrent Auto Precharge Micron SDRAM devices support concurrent auto precharge, which allows an access command (READ or WRITE) to another bank while an access command with auto pre- charge enabled is executing. Four cases where concurrent auto precharge occurs are ...
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WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): When a READ to bank m reg- isters, it will interrupt a WRITE on bank n, with the data-out appearing clocks later, (depending ...
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Table 7: Truth Table 2 – CKE Notes: 1-4; Notes appear below table. CKE CKE Current State n-1 n Power-Down Self Refresh L L Clock Suspend Deep Power-Down Power-Down Deep Power-Down L H Self Refresh Clock Suspend All Banks Idle ...
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Table 8: Truth Table 3 – Current State BanK n, Command to Bank n Notes: 1-6; notes appear below table. Current State CS# RAS# Any Idle Row Active ...
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Precharging All: Starts with registration of a PRECHARGE ALL command and ends when 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; ...
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Table 9: Truth Table 4 – Current State Bank n, Command to Bank m Notes: 1-6; notes appear below and on next page. Current State CS# RAS# Any Idle X X Row L L Activating, L ...
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READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge ...
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Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections ...
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Table 12: Electrical Characteristics and Recommended AC Operating Conditions Notes 11; notes appear on page 43 AC Characteristics Parameter Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level ...
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Table 13: AC Functional Characteristics Notes 11; notes appear on page 43 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode ...
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Table 15 Self Refresh Current Options DD Notes: 4; notes appear on page 43; V Temperature Compensated Self Refresh Parameter/Condition Self Refresh Current: CKE < 0.2V – 4 Banks Open Self Refresh Current: CKE < 0.2V – ...
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Notes 1. All voltages referenced This parameter is sampled. V 1.4V MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications ...
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The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including used to reduce the data rate. 24. Auto precharge ...
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Initialize and Load Mode Register Figure 31: Initialize and Load Mode Register 1.8/1.8V 54-ball VFBGA (8mm x 8mm) 54-ball VFBGA (8mm x 8mm) Lead-Free Notes: 1. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, ...
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Timing Diagrams Figure 32: Power-Down Mode T0 CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQML, DQMU A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles ...
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Figure 33: Clock Suspend Mode CLK CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQMU, DQML A0–A9, A11 2 COLUMN ...
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Figure 34: Auto Refresh Mode T0 CLK CKE t CKS t CMS COMMAND PRECHARGE DQMU, DQML A0-A9, A11 ALL BANKS A10 SINGLE BANK t AS BA0, BA1 BANK(S) High-Z DQ Precharge all active banks Notes: 1. Each AUTO REFRESH command ...
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Figure 35: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQMU, DQML A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all ...
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Figure 36: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 DISABLE ...
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Figure 37: READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQMU, DQML A0-A9, A11 ROW ROW A10 ...
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Figure 38: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
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Figure 39: Single READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
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Figure 40: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 t AS ...
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Figure 41: READ – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML COLUMN m 2 A0-A9, A11 ...
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Figure 42: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 t AS ...
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Figure 43: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 DISABLE ...
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Figure 44: WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ENABLE AUTO PRECHARGE ...
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Figure 45: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
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Figure 46: Single WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQMU, DQML A0-A9, A11 ROW ...
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Figure 47: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML COLUMN m 2 A0–A9, A11 ROW t ...
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Figure 48: Write – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
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Figure 49: Write – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ROW A10 t AS ...
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Package Dimensions Figure 50: 54-Ball FBGA (8mm x 8mm) 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS 0.42. BALL A9 6.40 3.20 ±0.05 3.20 ±0.05 ...