DS21458-W+ Maxim Integrated, DS21458-W+ Datasheet - Page 9

• Manufacturer Part Number: DS21458-W+
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS21458-W+

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CSBGA
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 3.3 V
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Part # Aliases: 90-21458+W00

DS21455/DS21458 Quad T1/E1/J1 Transceivers
1. DESCRIPTION
The DS21455 and DS21458 are quad monolithic devices featuring independent transceivers that can be
software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer,
HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured
for Intel or Motorola bus operations. The DS21455* is a direct replacement for the older DS21Q55 quad
MCM device. The DS21458, which comes in a smaller package (17mm CSBGA) and features an
improved controller interface, is software compatible with the older DS21Q55.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit
interface is responsible for generating the necessary waveshapes for driving the network and providing
the correct source impedance depending on the type of media used. T1 waveform generation includes
DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and data from the network. The receive sensitivity
adjusts automatically to the incoming signal and can be programmed for 0dB to 43dB or 0dB to 12dB for
E1 applications and 0dB to 15dB or 0dB to 36dB for T1 applications. The jitter attenuator removes phase
jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications)
and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI
coder/decoder for interfacing to optical networks.
On the transmit side, clock/data, and frame-sync signals are provided to the framer by the backplane
interface section. The framer inserts the appropriate synchronization framing patterns and alarm
information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression)
and AMI line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes
to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data
and frame-sync signals to the backplane interface section.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and
receive data via the framer block. The HDLC controllers can be assigned to any time slot, group of time
slots, portion of a time slot, or to FDL (T1) or Sa bits (E1). Each controller has 128-bit FIFOs, thus
reducing the amount of processor overhead required to manage the flow of data. In addition, built-in
support for reducing the processor time required handles SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system.
Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1
network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also
manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up
to eight transceivers (two DS21455s/DS21458s) to share a high-speed backplane.
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