DS21458-W+ Maxim Integrated, DS21458-W+ Datasheet - Page 4

• Manufacturer Part Number: DS21458-W+
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS21458-W+

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CSBGA
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 3.3 V
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Part # Aliases: 90-21458+W00

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15.1
15.2
15.3
15.4
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16.2
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17.2
18.1
20.1
20.2
20.3
20.4
22.1
22.2
23.1
23.2
23.3
24.1
24.2
24.3
24.4
24.5
15.1.1
15.1.2
15.2.1
15.2.2
15.3.1
15.3.2
17.1.1
17.1.2
17.2.1
17.2.2
17.2.3
20.1.1
20.1.2
20.2.1
20.2.2
24.2.1
24.3.1
24.3.2
24.3.3
24.3.4
24.3.5
I/O PIN CONFIGURATION OPTIONS......................................................................................................... 78
LOOPBACK CONFIGURATIONS ............................................................................................................... 80
ERROR COUNT REGISTERS..................................................................................................................... 85
DS0 MONITORING FUNCTION .................................................................................................................. 91
SIGNALING OPERATION ........................................................................................................................... 93
PER-CHANNEL IDLE CODE GENERATION ........................................................................................... 108
CHANNEL BLOCKING REGISTERS........................................................................................................ 113
ELASTIC STORES OPERATION.............................................................................................................. 116
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)............................................................... 122
T1 BIT ORIENTED CODE (BOC) CONTROLLER.................................................................................... 123
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) ....................................... 127
HDLC CONTROLLERS ............................................................................................................................. 141
P
L
P
F
E-B
T
R
R
T
I
R
T
E
M
T
R
H
I
I
B
HDLC C
HDLC M
R
L
DLE
NTERNAL
NTERNAL
INE
EGACY
RAMES
RANSMIT
RANSMIT
RANSMIT
RANSMIT
ER
ATH
LASTIC
ASIC
ECEIVE
ECEIVE
ECEIVE
ECEIVE
ARDWARE
ECEIVE
INIMUM
IT
-C
C
C
C
C
O
ODE
HANNEL
ODE
T1 Operation....................................................................................................................86
E1 Operation ...................................................................................................................86
T1 Operation....................................................................................................................88
E1 Operation ...................................................................................................................88
T1 Operation....................................................................................................................89
E1 Operation ...................................................................................................................89
Processor-Based Receive Signaling............................................................................94
Hardware-Based Receive Signaling ............................................................................94
Processor-Based Transmit Signaling ........................................................................100
Software Signaling Insertion Enable Registers, E1 CAS Mode.............................104
Software Signaling Insertion Enable Registers, T1 Mode ......................................106
T1 Mode .........................................................................................................................119
E1 Mode .........................................................................................................................119
T1 Mode .........................................................................................................................120
E1 Mode .........................................................................................................................120
FIFO Control ..................................................................................................................145
Receive...........................................................................................................................146
Transmit .........................................................................................................................148
FIFO Information...........................................................................................................153
Receive Packet Bytes Available .................................................................................153
HDLC FIFOS .................................................................................................................154
ODE
OUNTER
PERATION
FDL S
O
S
ONFIGURATION
-D
APPING
DS0 M
S
S
BOC................................................................................................................. 123
HDLC C
R
R
TORES
DS0 M
S
S
BOC............................................................................................................... 123
UT
IGNALING
IDE
P
V
ELAY
EGISTER
EGISTER
S
IGNALING
IDE
V
ROGRAMMING
IOLATION
CHEME
O
IOLATION
................................................................................................................. 119
P
UPPORT
F
............................................................................................................... 120
ONITOR
.............................................................................................................. 146
R
AYLOAD
M
S
I
ONITOR
ODE
EGISTER
NITIALIZATION
D
YNC
ODE
.......................................................................................................... 93
ETAILS
S
S
(M
...................................................................................................... 100
CHEME
CHEME
C
E
C
C
(T1 M
................................................................................................... 121
................................................................................................... 143
ETHOD
OUNT
XAMPLE
R
L
OUNT
OUNT
R
EGISTERS
OOPBACK
E
(EBCR)................................................................................... 90
EGISTERS
............................................................................................. 141
XAMPLES
B
B
ODE
R
R
R
1) .................................................................................... 127
ASED
ASED
EGISTER
...................................................................................... 120
...................................................................................... 155
EGISTER
EGISTER
).................................................................................. 155
.................................................................................. 83
.................................................................................. 92
O
O
................................................................................ 91
............................................................................. 109
N
N
(LCVCR)............................................................ 86
D
CRC-4 M
(PCVCR) .......................................................... 88
(FOSCR) .......................................................... 89
OUBLE
4 of 269
-F
ULTIFRAME
RAME
(M
ETHOD
DS21455/DS21458 Quad T1/E1/J1 Transceivers
(M
ETHOD
2) ............................. 127
3) ...................... 130