DS21458-W+ Maxim Integrated, DS21458-W+ Datasheet - Page 27

• Manufacturer Part Number: DS21458-W+
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS21458-W+

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CSBGA
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 3.3 V
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Part # Aliases: 90-21458+W00

Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left
unconnected.
5.6 Line Interface Pins
Signal Name:
Signal Description:
Signal Type:
A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and
E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in
T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock.
Signal Name:
Signal Description:
Signal Type:
A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and
E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in
T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock.
Signal Name:
Signal Description:
Signal Type:
This is a dual function pin depending on the state of the LTS bit in the LBCR register (LBCR.7).
LTS = 0: In this mode the LIUC/TPD pin, along with the LIUC bit of the LBCR register controls the connection between the
framer and the LIU. This function is only available on the DS21455. See the LIUC bit description in Section
Table
LTS = 1: In this mode the LIUC/TPD pin along with the TPD bit in the LIC1 register (LIC1.0) controls the state of the
Transmit Power-Down function. See the TPD bit description in Section
Signal Name:
Signal Description:
Signal Type:
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the network. See Section
Signal Name:
Signal Description:
Signal Type:
Analog line-driver outputs. These pins connect via a 1:2 step-up transformer to the network. See Section
14-1.
JTCLK
IEEE 1149.1 Test Clock Signal
Input
JTDI
IEEE 1149.1 Test Data Input
Input
JTDO
IEEE 1149.1 Test Data Output
Output
MCLK1
Master Clock Input for Transceivers 1 and 2
Input
MCLK2
Master Clock Input for Transceivers 3 and 4
Input
LIUC/TPD (DS21455), TPD (DS21458)
Line Interface Unit Connect/Transmit Power-Down
Input
RTIP and RRING
Receive Tip and Ring
Input
TTIP and TRING
Transmit Tip and Ring
Output
27 of 269
25
DS21455/DS21458 Quad T1/E1/J1 Transceivers
and
Table
25-1.
25
for details.
14
25
and
for details.