DS21458-W+ Maxim Integrated, DS21458-W+ Datasheet
DS21458-W+
Specifications of DS21458-W+
Related parts for DS21458-W+
DS21458-W+ Summary of contents
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... DS21Q55 quad MCM device. The DS21458 smaller package (17mm CSBGA) and featuring an improved controller interface, is software compatible with the older DS21Q55. *The JTAG function on the DS21455/DS21458 is a single controller for all four transceivers, unlike the DS21Q55, which has a JTAG controller-per-transceiver architecture. APPLICATIONS ...
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... Removed CCR4.0, CCR4.1, CCR4.2, and CCR4.3 bits from CCR4. These were 101304 listed as User Programmable Outputs but these do not exist on the DS21458 or the DS21455. Removed references to TESO and TDATA in the pin description list, as these pins 042105 are not available on the DS21455/DS21458 ...
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... Auto RAI ...........................................................................................................................68 11.2.3 Auto E-Bit .........................................................................................................................68 11.2.4 G.706 CRC-4 Interworking ............................................................................................68 11 NFORMATION EGISTERS 12. COMMON CONTROL AND STATUS REGISTERS.................................................................................... 71 TABLE OF CONTENTS B .............................................................................. 14 US ................................................................................................... 17 .......................................................................................... 17 P ........................................................................................ 24 INS B .............................................................................. ........................................................................................ 26 INS .................................................................................................. 51 R ................................................................................ 51 EGISTERS ................................................................................................... 53 ........................................................................................... 58 D .............................................................. 59 ETECTION - .................................................. 60 ILLIWATT ODE ENERATION ............................................................................................... 62 .................................................................................................. 64 ....................................................................................... 68 ............................................................................................. 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
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... OOPBACK R (LCVCR)............................................................ 86 EGISTER R (PCVCR) .......................................................... 88 OUNT EGISTER R (FOSCR) .......................................................... 89 OUNT EGISTER (EBCR)................................................................................... 90 R ................................................................................ 91 EGISTERS .................................................................................. 92 EGISTERS E ............................................................................. 109 XAMPLES ...................................................................................... 120 1) .................................................................................... 127 ASED N OUBLE RAME B O CRC-4 M ASED N ULTIFRAME ............................................................................................. 141 ...................................................................................... 155 ).................................................................................. 155 ODE 4 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers 2) ............................. 127 ETHOD (M 3) ...................... 130 ETHOD ...
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... ULTIPLEXED US HARACTERISTICS 38 ONMULTIPLEXED US 38 ECEIVE IDE HARACTERISTICS 38 RANSMIT HARACTERISTICS 39. PACKAGE INFORMATION ....................................................................................................................... 269 ) O ............................................................................ 163 PTION ............................................................................................... 164 ................................................................................................ 173 .......................................................................................... 175 ........................................................................................ 187 S ..................................................................................... 192 ET ................................................................................................. 194 ....................................................................................... 197 ........................................................................................... 199 ............................................................................................... 199 ............................................................................................ 222 ............................................................................................... 222 ........................................................................ 253 .................................................................. 256 HARACTERISTICS ............................................................................... 259 ..................................................................................... 265 5 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
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... Figure 3-1. DS21458 Block Diagram ......................................................................................................................... 15 Figure 3-2. DS21455 Block Diagram ......................................................................................................................... 16 Figure 4-1. DS21455 Framer/LIU Interim Signals ..................................................................................................... 18 Figure 4-2. DS21458 Framer/LIU Interim Signals ..................................................................................................... 19 Figure 5-1. DS21455 Pin Diagram, 27mm BGA........................................................................................................ 39 Figure 5-2. DS21458 Pin Diagram, 17mm CSBGA................................................................................................... 40 Figure 8-1. Programming Sequence.......................................................................................................................... 48 Figure 9-1. Clock Map ............................................................................................................................................... 52 Figure 14-1. Normal Signal Flow Diagram ................................................................................................................ 80 Figure 17-1 ...
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... Figure 38-10. Receive Side Timing, Elastic Store Enabled (T1 Mode) ................................................................... 262 Figure 38-11. Receive Side Timing, Elastic Store Enabled (E1 Mode)................................................................... 263 Figure 38-12. Receive Line Interface Timing........................................................................................................... 264 Figure 38-13. Transmit Side Timing ........................................................................................................................ 266 Figure 38-14. Transmit Side Timing, Elastic Store Enabled.................................................................................... 267 Figure 38-15. Transmit Line Interface Timing.......................................................................................................... 268 DS21455/DS21458 Quad T1/E1/J1 Transceivers 7 of 269 ...
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... Table 5-1. DS21455 Pin Description ......................................................................................................................... 29 Table 5-2. DS21458 Pin Description ......................................................................................................................... 34 Table 6-1. Register Map Sorted By Address ............................................................................................................. 41 Table 10-1. T1 Alarm Criteria .................................................................................................................................... 63 Table 11-1. E1 Sync/Resync Criteria......................................................................................................................... 65 Table 11-2. Auto E-Bit Conditions ............................................................................................................................. 68 Table 11-3. E1 Alarm Criteria .................................................................................................................................... 70 Table 14-1. LIUC Control........................................................................................................................................... 82 Table 15-1. T1 Line Code Violation Counting Options .............................................................................................. 86 Table 15-2. E1 Line Code Violation Counting Options .............................................................................................. 86 Table 15-3 ...
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... HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21455 direct replacement for the older DS21Q55 quad MCM device. The DS21458, which comes in a smaller package (17mm CSBGA) and features an improved controller interface, is software compatible with the older DS21Q55. ...
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... The parallel port provides access for control and configuration of all the DS21455/DS21458’s features. The Extended System Information Bus (ESIB) function allows up to eight transceivers, two DS21455s or two DS21458s to be accessed via a single read for interrupt status or other user-selectable alarm status information. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection ...
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... FEATURE HIGHLIGHTS 2.1 General DS21455: 27mm, 1.27 pitch BGA, compatible replacement for the DS21Q55 DS21458: 17mm, 1.00 pitch CSBGA 3.3V supply with 5V tolerant inputs and outputs Evaluation kits IEEE 1149.1 JTAG-boundary scan Driver source code available from the factory 2.2 Line Interface ...
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... Receive-signaling freeze on loss of sync, carrier loss, or frame slip Hardware pins to indicate carrier loss and signaling freeze Automatic RAI generation to ETS 300 011 specifications Expanded access to Sa and Si bits Option to extend carrier-loss criteria to a 1ms period as per ETS 300 233 DS21455/DS21458 Quad T1/E1/J1 Transceivers 12 of 269 ...
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... Insertion options include continuous and absolute number with selectable insertion rates Total-bit and errored-bit counters Payload Error Insertion Errors can be inserted over the entire frame or selected channels F-bit corruption for line testing Loopbacks (remote, local, analog, and per-channel payload loopback) DS21455/DS21458 Quad T1/E1/J1 Transceivers 13 of 269 ...
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... Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last. The term “locked” is used to refer to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component). DS21455/DS21458 Quad T1/E1/J1 Transceivers 14 of 269 ...
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... BLOCK DIAGRAM Figure 3-1 shows a simplified block diagram highlighting the major components of the DS21458 and DS21455. Figure 3-1. DS21458 Block Diagram MCLK2 MCLK1 MASTER CLOCK LOCAL RECEIVE LOOP RTIP LIU BACK JITTER CLOCK & DATA ATTEN. RECOVERY RRING PATH TRANSMIT LIU TTIP JITTER ATTEN ...
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... CLOCK & DATA RECOVERY RRING TRANSMIT OR RECEIVE TRANSMIT LIU TTIP WAVESHAPE GENERATION TRING LIUC/TPD JTAG JTDO JTCLK JTMS ESIBS0 JTDI JTRST DS21455/DS21458 Quad T1/E1/J1 Transceivers RPOSO RPOSI RNEGO RNEGI RCLKO RCLKI 2 HDLCs MUX JITTER ATTEN. DS21455 PATH JITTER MUX ATTEN. TPOSI TPOSI TPOSO ...
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... DS21455: The three ESIB signals are brought out for each transceiver. The user must externally configure the ESIB group. DS21458: The ESIB signals are internally bused and only a single set of signals are brought out to enable the connection of another DS21458 into an 8-port ESIB. ...
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... RCLKI MUX Rx LIU Tx MUX LIU TPOSI TNEGI TCLKI RPOSO RPOSI RNEGO RNEGI RCLKO RCLKI MUX Rx LIU Tx MUX LIU TPOSI TNEGI TCLKI DS21455/DS21458 Quad T1/E1/J1 Transceivers #1 Rx FRAMER Rx LIU Tx FRAMER Tx LIU TPOSO TNEGO TCLKO #3 Rx FRAMER Rx LIU Tx FRAMER Tx LIU TPOSO TNEGO LIUC TCLKO ...
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... Figure 4-2. DS21458 Framer/LIU Interim Signals RPOSO1 RNEGO1 RCLKO1 Rx LIU Tx LIU TPOSO1 TNEGO1 TCLKO1 RPOSO3 RNEGO3 RCLKO3 Rx LIU Tx LIU TPOSO3 TNEGO3 TCLKO3 DS21455/DS21458 Quad T1/E1/J1 Transceivers RPOSO2 RNEGO2 RCLKO2 # LIU FRAMER Tx Tx FRAMER LIU RPOSO4 RNEGO4 RCLKO4 # FRAMER LIU Tx Tx FRAMER ...
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... Transmit Link Data Signal Type: Input If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs- bit position (D4) or the Z-bit position (ZBTSI) or any combination of the Sa bit positions (E1). DS21455/DS21458 Quad T1/E1/J1 Transceivers 20 of 269 ...
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... Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of this function. TPOSI and TNEGI can be tied together in NRZ applications. DS21455/DS21458 Quad T1/E1/J1 Transceivers 21 of 269 ...
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... Signal Name: RSER Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled. DS21455/DS21458 Quad T1/E1/J1 Transceivers 22 of 269 ...
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... TCLK pin has not been toggled for 5s. Signal Name: RSIGF Signal Description: Receive Signaling Freeze Signal Type: Output Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition. DS21455/DS21458 Quad T1/E1/J1 Transceivers 23 of 269 ...
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... Signal Type: Input A dual-function pin. A zero-to-one transition issues a hardware reset to the DS21455/DS21458 register set. A reset clears all configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will tri-state all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing. ...
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... Signal Type: Input In nonmultiplexed bus operation (MUX = 0), it serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low. Signal Name: A8 and A9 (DS21458 Only) Signal Description: Address Bus Signal Type: Input Upper address pins for nonmultiplexed (MUX = 0), and multiplexed (MUX = 1) bus operation. ...
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... Signal Description: Extended System Information Bus Read Signal Type: Input/Output Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System Information Bus (ESIB) section for more details. 5.5 JTAG Test Access Port Pins Signal Name: JTRST Signal Description: IEEE 1149 ...
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... A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock. ...
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... Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0.0V. Should be tied to DVSS and TVSS. Signal Name: TVSS Signal Description: Transmit Analog Signal Ground Signal Type: Supply 0.0V. Should be tied to DVSS and RVSS. DS21455/DS21458 Quad T1/E1/J1 Transceivers 28 of 269 ...
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... A20 DVSS — B11 DVSS — A5 DVSS — DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Address Bus Bit 0 (Lsb) Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Bus Bit 7 (Msb)/Address Latch Enable ...
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... A2 RFSYNC3 O V14 RFSYNC4 O F1 RLCLK1 O DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Digital Signal Ground Digital Signal Ground Digital Signal Ground Digital Signal Ground Digital Signal Ground Extended System Information Bus Read for Transceiver 1 Extended System Information Bus Read for Transceiver 2 Extended System Information Bus Read for Transceiver 3 ...
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... RSYNC4 I/O H1 RSYSCLK1 I F17 RSYSCLK2 I DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Receive Link Clock for Transceiver 2 Receive Link Clock for Transceiver 3 Receive Link Clock for Transceiver 4 Receive Link Data for Transceiver 1 Receive Link Data for Transceiver 2 Receive Link Data for Transceiver 3 Receive Link Data for Transceiver 4 ...
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... O B20 TNEGO2 O D9 TNEGO3 O DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Receive System Clock for Transceiver 3 Receive System Clock for Transceiver 4 Receive Analog Tip Input for Transceiver 1 Receive Analog Tip Input for Transceiver 2 Receive Analog Tip Input for Transceiver 3 Receive Analog Tip Input for Transceiver 4 ...
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... U18 TVSS — (R/W) DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Transmit Negative-Data Output from Framer on Transceiver 4 Transmit Positive-Data Input for the LIU on Transceiver 1 Transmit Positive-Data Input for the LIU on Transceiver 2 Transmit Positive-Data Input for the LIU on Transceiver 3 Transmit Positive-Data Input for the LIU on Transceiver 4 ...
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... Table 5-2. DS21458 Pin Description PIN NAME H2 A0 E10 A7/ALE (AS J11 A9 J5 BPCLK1 H13 BPCLK2 E8 BPCLK3 N9 BPCLK4 B10 BTS D0/AD0 D10 D1/AD1 N8 D2/AD2 P7 D3/AD3 M7 D4/AD4 R7 D5/AD5 G1 D6/AD6 G3 D7/AD7 P4 DVDD P5 DVDD P6 DVDD C11 DVDD C12 ...
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... O E6 RMSYNC3 O M10 RMSYNC4 O H10 Unused I DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Extended System Information Bus 1 Active-Low Interrupt for All Four Transceivers JTAG Clock JTAG Data Input JTAG Data Output JTAG Test Mode Select JTAG Reset Transmit Power-Down Enable Master Clock for Transceiver 1 and Transceiver 3 ...
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... T13 RVSS — T9 RVSS — DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Receive Negative Data from the LIU on Transceiver 1 Receive Negative Data from the LIU on Transceiver 2 Receive Negative Data from the LIU on Transceiver 3 Receive Negative Data from the LIU on Transceiver 4 Connect to VSS for Proper Operation ...
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... TRING3 O D2 TRING3 O N15 TRING4 O DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Transmit Channel Block for Transceiver 1 Transmit Channel Block for Transceiver 2 Transmit Channel Block for Transceiver 3 Transmit Channel Block for Transceiver 4 Transmit Channel Clock for Transceiver 1 Transmit Channel Clock for Transceiver 2 Transmit Channel Clock for Transceiver 3 ...
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... TVSS — M16 TVSS — (R/W) DS21455/DS21458 Quad T1/E1/J1 Transceivers FUNCTION Transmit Analog Ring Output for Transceiver 4 Transmit Serial Data for Transceiver 1 Transmit Serial Data for Transceiver 2 Transmit Serial Data for Transceiver 3 Transmit Serial Data for Transceiver 4 Transmit Signaling Input for Transceiver 1 ...
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... D0/AD0 TCLKI1 TPOSO1 A4 ESIBS11 TCHCLK1 RLOS4 ESIBS01 TCLKO1 DVSS TSER1 TSIG1 TSYSCLK1 TSSYNC1 TRING3 TTIP4 TRING4 TCLK1 RTIP1 RRING1 39 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers RLCLK2 RLINK2 CS2 RCLKI2 RPOSO2 DVSS DVDD RCLK2 RPOSI2 RNEGO2 RSIG2 ESIBS12 DVDD EISBRD2 ...
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... Figure 5-2. DS21458 Pin Diagram, 17mm CSBGA TNEGO3 RCLKO3 TSSYNC3 RVSS B TPOSO3 TCLKO3 TSYNC3 TCHCLK3 TTIP3 TTIP3 RLINK3 TLCLK3 C D TRING3 TRING3 DVDD DVSS TVSS TVSS DVDD DVSS E F TVDD TVDD DVDD DVSS A7/ALE D6/AD6 D7/AD7 A3 G (AS) H RVDD A0 A2 ...
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... Status Register 7 23 Interrupt Mask Register 7 24 Status Register 8 25 Interrupt Mask Register 8 26 Status Register 9 27 Interrupt Mask Register 9 28 Per-Channel Pointer Register 29 Per-Channel Data Register 1 DS21455/DS21458 Quad T1/E1/J1 Transceivers REGISTER NAME 41 of 269 REGISTER PAGE ABBREVIATION MSTRREG 49 IOCR1 78 IOCR2 79 T1RCR1 53 T1RCR2 ...
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... Transmit Signaling Register 9 59 Transmit Signaling Register 10 5A Transmit Signaling Register 11 5B Transmit Signaling Register 12 5C Transmit Signaling Register 13 5D Transmit Signaling Register 14 5E Transmit Signaling Register 15 DS21455/DS21458 Quad T1/E1/J1 Transceivers REGISTER ABBREVIATION PCDR2 PCDR3 PCDR4 INFO4 INFO5 INFO6 INFO7 H1RC H2RC E1RCR1 ...
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... Transmit Channel Blocking Register 2 8E Transmit Channel Blocking Register 3 8F Transmit Channel Blocking Register 4 90 HDLC #1 Transmit Control 91 HDLC #1 FIFO Control 92 HDLC #1 Receive Channel Select 1 93 HDLC #1 Receive Channel Select 2 DS21455/DS21458 Quad T1/E1/J1 Transceivers REGISTER ABBREVIATION TS16 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 ...
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... Receive FDL Match Register 2 C4 Unused. Must be set = 00h for proper operation C5 Interleave Bus Operation Control Register C6 Receive Align Frame Register C7 Receive Nonalign Frame Register C8 Receive Si Align Frame DS21455/DS21458 Quad T1/E1/J1 Transceivers REGISTER ABBREVIATION H1RCS3 H1RCS4 H1RTSBS H1TCS1 H1TCS2 H1TCS3 H1TCS4 H1TTSBS ...
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... Number Of Errors Left 2 F0 Unused. Must be set = 00h for proper operation F1 Pulse Shape Adjustment 1 F2 Pulse Shape Adjustment 2 F3–F9, FA–FF Unused. Must be set = 00h for proper operation DS21455/DS21458 Quad T1/E1/J1 Transceivers REGISTER NAME 45 of 269 REGISTER PAGE ABBREVIATION RSiNAF 131 RRA ...
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... Bit 4/BERT Receive Channel Select (BRCS). Bit 5/Receive Fractional Channel Select (RFCS). Bit 6/Receive Signaling Reinsertion Channel Select (RSRCS). Bit 7/Receive Signaling All Ones Insertion Channel Select (RSAOICS). DS21455/DS21458 Quad T1/E1/J1 Transceivers Write 11h to PCPR Write 00h to PCDR1 Write 0fh to PCDR2 Write 18h to PCDR3 ...
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... Register Address: 2Bh Bit # 7 6 Name Default CH24 CH23 Register Name: PCDR4 Register Description: Per-Channel Data Register 4 Register Address: 2Ch Bit # 7 6 Name Default CH32 CH31 DS21455/DS21458 Quad T1/E1/J1 Transceivers CH6 CH5 CH4 CH14 CH13 CH12 CH22 CH21 CH20 ...
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... PROGRAMMING MODEL The DS21455/DS21458 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the device, selecting operation in the master mode register, enabling functions, and enabling the common functions. The act of resetting the device automatically clears all configuration and status registers ...
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... The LIRST (LIC2.6) should be toggled from zero to one to reset the line interface circuitry. (It will take the DS21455/DS21458 about 40ms to recover from the LIRST bit being toggled.) Finally, after the TSYSCLK and RSYSCLK inputs are stable, the receive and transmit elastic stores should be reset (this step can be skipped if the elastic stores are disabled) ...
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... The user will always proceed a read of any of the status registers with a write. The byte written to the register will inform the DS21455/DS21458 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on ...
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... Name SR8 SR7 Default 0 0 Register Name: IIR2 Register Description: Interrupt Information Register 2 Register Address: 15h Bit # 7 6 Name — — Default 0 0 DS21455/DS21458 Quad T1/E1/J1 Transceivers SR6 SR5 SR4 SR3 — — — 269 2 1 ...
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... CLOCK MAP Figure 9-1 shows the clock map of the DS21455/DS21458. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity ...
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... T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS21455/DS21458 is configured via a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration ...
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... SLC–96 disabled 1 = SLC–96 enabled Bit 5/Receive B8ZS Enable (RB8ZS B8ZS disabled 1 = B8ZS enabled Bit 6/Receive Frame Mode Select (RFM framing mode 1 = ESF framing mode Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers RB8ZS RSLC96 RZSE 0 0 ...
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... Bit 6/Transmit F-Bit Pass Through (TFPT bits sourced internally bits sampled at TSER Bit 7/Transmit Japanese CRC6 Enable (TJC use ANSI/AT&T/ITU CRC6 calculation (normal operation use Japanese standard JT–G704 CRC6 calculation DS21455/DS21458 Quad T1/E1/J1 Transceivers TCPT TSSE GB7S ...
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... Must be set to one to source the Fs pattern from the TFDL register. See D4/SLC–96 Operation for details SLC–96/Fs-bit insertion disabled 1 = SLC–96/Fs-bit insertion enabled Bit 7/Transmit B8ZS Enable (TB8ZS B8ZS disabled 1 = B8ZS enabled DS21455/DS21458 Quad T1/E1/J1 Transceivers TZSE FBCT2 ...
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... ESF RAI-CI code 1 = transmit the ESF RAI-CI code Bit 5/Unused, must be set to zero for proper operation. Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers — ...
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... T1TCR2.0 bits are set to one, then all 24 T1 channels will have bit 7 stuffing performed on them, regardless of how the SSIEx registers are programmed. In this manner, the SSIEx registers are only affecting channels that are to have robbed-bit signaling inserted into them. DS21455/DS21458 Quad T1/E1/J1 Transceivers 58 of 269 ...
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... AIS-CI and RAI-CI Generation and Detection The DS21455/DS21458 can transmit and detect the RAI-CI and AIS-CI codes in T1 mode. These codes are compatible with and do not interfere with the standard RAI (Yellow) and AIS (Blue) alarms. These codes are defined in ANSI T1.403. ...
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... Each bit in the T1RDMRx registers represents a particular channel bit is set to a one, then the receive data in that channel will be replaced with the digital-milliwatt code bit is set to zero, no replacement occurs. DS21455/DS21458 Quad T1/E1/J1 Transceivers 60 of 269 ...
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... CH23 Default 0 0 Bits 0 to 7/Receive Digital-Milliwatt Enable for Channels (CH17 to CH24 not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code DS21455/DS21458 Quad T1/E1/J1 Transceivers CH6 CH5 CH4 ...
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... Bit 6/Transmit Pulse Density Violation Event (TPDV). Set when the transmit data stream does not meet the ANSI T1.403 requirements for pulse density. Bit 7/Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density. DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
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... The blue alarm criteria in the DS21455/DS21458 have been set to achieve this performance recommended that the RBL bit be qualified with the RLOS bit. ...
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... E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS21455/DS21458 is configured via a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration ...
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... Sa7-bit position. See the Functional Timing Diagrams section for details. Bit 7/Sa8-Bit Select (Sa8S). Set to one to have RLCLK pulse at the Sa8-bit position; set to zero to force RLCLK low during Sa8-bit position. See the Functional Timing Diagrams section for details. DS21455/DS21458 Quad T1/E1/J1 Transceivers RESYNC CRITERIA Three consecutive incorrect FAS received Alternate: (E1RCR1 ...
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... SSIEx registers and the THSCS function in the PCPR register 1 = source time slot 16 from TS1 to TS16 registers Bit 7/Transmit Time Slot 0 Pass Through (TFPT FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER DS21455/DS21458 Quad T1/E1/J1 Transceivers TUA1 ...
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... Bit 6/Sa7-Bit Select (Sa7S). Set to one to source the Sa7 bit from the TLINK pin; set to zero to not source the Sa7 bit. See the Functional Timing Diagrams section for details. Bit 7/Sa8-Bit Select (Sa8S). Set to one to source the Sa8 bit from the TLINK pin; set to zero to not source the Sa8 bit. See the Functional Timing Diagrams section for details. DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
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... FAS synchronization (if CRC-4 is enabled). If any one (or more) of the above conditions is present, then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm will be transmitted if the DS21455/DS21458 cannot find CRC-4 multiframe synchronization within 400ms as per G.706. ...
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... CRC-4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. The CRC-4 sync counter will rollover. CSC0 is the LSB of the 6-bit counter. (Note: The second LSB, CSC1, is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.) DS21455/DS21458 Quad T1/E1/J1 Transceivers — ...
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... Bit 6 of time slot 16 in frame 0 has been set for two consecutive RDMA multiframes Two out of three Sa7 bits are V52LNK zero DS21455/DS21458 Quad T1/E1/J1 Transceivers CLEAR CRITERIA In 255-bit times, at least 32 ones are received Bit 3 of nonalign frame set to zero for three consecutive occasions ...
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... CRC-4 generation and insertion operates in normal mode 1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method Bit 7/MCLK Source (MCLKS). Selects the source of MCLK MCLK is sourced from the MCLK pin 1 = MCLK is sourced from the TSYSCLK pin DS21455/DS21458 Quad T1/E1/J1 Transceivers SIE ODM — ...
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... IDO is the LSB of a decimal code that represents the chip revision. Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the device ID. The device IDs for the DS21458 and DS21455 are shown in the table below. DS21458 ...
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... Bit 5/Framer Receive Carrier Loss Condition Clear (FRCLC interrupt masked 1 = interrupt enabled Bit 6/Receive Unframed All Ones Condition Clear Event (RUA1C interrupt masked 1 = interrupt enabled Bit 7/Receive Yellow Alarm Clear Event (RYELC interrupt masked 1 = interrupt enabled DS21455/DS21458 Quad T1/E1/J1 Transceivers FRCLC RLOSC RYEL 0 0 ...
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... See the Programmable In-Band Loop Code Generation and Detection section for details. Bit 7/Spare Code Detected Condition (LSPARE). (T1 only) Set when the spare code as defined in the RSCD1/2 registers is being received. See the Programmable In-Band Loop Code Generation and Detection section for details. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
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... Bit 6/Loop-Down Code Detected Condition (LDN interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges Bit 7/Spare Code Detected Condition (LSPARE interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges DS21455/DS21458 Quad T1/E1/J1 Transceivers LUP LOTC LORC ...
Page 76
... Bit 6/Receive Signaling All Ones Event (RSA1) (E1 Only). Set when the contents of time slot 16 contains fewer than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Bit 7/Receive AIS-CI Event (RAIS-CI) (T1 Only). Set when the receiver detects the AIS-CI pattern as defined in ANSI T1.403. DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 77
... Bit 5/Receive Signaling All-Zeros Event (RSA0 interrupt masked 1 = interrupt enabled Bit 6/Receive Signaling All-Ones Event (RSA1 interrupt masked 1 = interrupt enabled Bit 7/Receive AIS-CI Event (RAIS-CI interrupt masked 1 = interrupt enabled DS21455/DS21458 Quad T1/E1/J1 Transceivers RSA0 TMF TAF 269 ...
Page 78
... Bit 7/RSYNC Multiframe Skip Control (RSMS). Useful in framing format conversions from D4 to ESF. This function is not available when the receive-side elastic store is enabled. RSYNC must be set to output multiframe pulses (IOCR1 and IOCR1 RSYNC will output a pulse at every multiframe 1 = RSYNC will output a pulse at every other multiframe DS21455/DS21458 Quad T1/E1/J1 Transceivers RSMS1 ...
Page 79
... Bit 4/TSYNC Invert (TSYNCINV inversion 1 = invert Bit 5/RSYNC Invert (RSYNCINV inversion 1 = invert Bit 6/TCLK Invert (TCLKINV inversion 1 = invert Bit 7/RCLK Invert (RCLKINV inversion 1 = invert DS21455/DS21458 Quad T1/E1/J1 Transceivers RSYNCINV TSYNCINV TSSYNCINV 269 ...
Page 80
... LOOPBACK CONFIGURATIONS The DS21455/DS21458 have four loopback configurations including Framer, Payload, Local, and Remote loopback. Figure 14-1 Payload loopback may be done on a per-channel basis if both the transmit and receive paths are synchronous (RCLK = TCLK and RSYNC = TSYNC). See Section 14.1. Figure 14-1. Normal Signal Flow Diagram ...
Page 81
... RECEIVE LIU TRANSMIT LIU JITTER RECEIVE ATTENUATOR FRAMER JITTER TRANSMIT ATTENUATOR FRAMER JITTER ATTENUATOR JITTER ATTENUATOR REMOTE LOOPBACK 81 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers BACKPLANE I/F BACKPLANE I/F RECEIVE BACKPLANE FRAMER I/F TRANSMIT BACKPLANE FRAMER I/F ...
Page 82
... Bit 5/Unused, must be set to zero for proper operation. Bit 6/Unused, must be set to zero for proper operation. Bit 7/LIUC/TPD Pin Function Select (LTS). This bit selects the function the of the LIUC/TPD pin. On the DS21458, this bit should always be set = LIUC/TPD pin functions as the LIUC control (This function is not available on the DS21458) ...
Page 83
... Register Address: 4Ch Bit # 7 6 Name CH16 CH15 Default 0 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels (CH9 to CH16 loopback disabled 1 = enable loopback. Source data from the corresponding receive channel DS21455/DS21458 Quad T1/E1/J1 Transceivers CH6 CH5 CH4 CH14 ...
Page 84
... Register Address: 4Eh Bit # 7 6 Name CH32 CH31 Default 0 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels (CH25 to CH32 loopback disabled 1 = enable loopback. Source data from the corresponding receive channel DS21455/DS21458 Quad T1/E1/J1 Transceivers CH22 CH21 CH20 CH30 ...
Page 85
... ERROR COUNT REGISTERS The DS21455/DS21458 contain four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62ms (E1 mode only) or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers ...
Page 86
... The counter saturates at 65,535 and will not rollover. The bit error rate line would have to be greater than 10** -2 before the VCR would saturate. Table 15-2. E1 Line Code Violation Counting Options E1 CODE VIOLATION SELECT (ERCNT. DS21455/DS21458 Quad T1/E1/J1 Transceivers B8ZS ENABLED? WHAT IS COUNTED IN THE LCVCRs (T1RCR2.5) No BPVs No ...
Page 87
... Bits 0 to 7/Line Code Violation Counter Bits (LCVC0 to LCVC7). LCV0 is the LSB of the 16-bit code violation count LCVC13 LCVC12 LCVC11 LCVC5 LCVC4 LCVC3 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers LCVC10 LCVC9 LCCV8 LCVC2 LCVC1 LCVC0 ...
Page 88
... Errors in the Ft Pattern Yes Errors in Both the Ft and Fs Patterns Don’t Care Errors in the CRC6 Codewords PCVC13 PCVC12 PCVC11 PCVC5 PCVC4 PCVC3 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers PCVC10 PCVC9 PCVC8 PCVC2 PCVC1 PCVC0 ...
Page 89
... CAS or CRC-4 multiframe level. Since the maximum FAS word error count in a one-second period is 4000, this counter cannot saturate. The FOSCR1 (FOSCR1) is the most significant word and FOSCR2 is the least significant word of a 16- bit counter that records frames out of sync. DS21455/DS21458 Quad T1/E1/J1 Transceivers (ERCNT.1) MOS Number of Multiframes Out of Sync ...
Page 90
... Register Description: E-Bit Count Register 2 Register Address: 49h Bit # 7 6 Name EB7 EB6 Default 0 0 Bits 0 to 7/E-Bit Counter Bits (EB0 to EB7). EB0 is the LSB of the 16-bit E-bit count. DS21455/DS21458 Quad T1/E1/J1 Transceivers FOS13 FOS12 FOS11 FOS10 FOS5 ...
Page 91
... DS0 MONITORING FUNCTION The DS21455/DS21458 can monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set ...
Page 92
... Name B1 B2 Default 0 0 Bits 0 to 7/Receive DS0 Channel Bits (B1 to B8). Receive-channel data that has been selected by the receive-channel monitor-select register the LSB of the DS0 channel (last bit to be received). DS21455/DS21458 Quad T1/E1/J1 Transceivers — RCM4 RCM3 RCM2 ...
Page 93
... RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be used simultaneously. 17.1 Receive Signaling Figure 17-1. Simplified Diagram of Receive Signaling Path T1/E1 DATA STREAM SIGNALING EXTRACTION RECEIVE SIGNALING REGISTERS CHANGE OF STATE INDICATION REGISTERS DS21455/DS21458 Quad T1/E1/J1 Transceivers PER-CHANNEL CONTROL ALL RSER ONES RE-INSERTION RSYNC CONTROL SIGNALING RSIG BUFFERS ...
Page 94
... Change Of State In order to avoid constant monitoring of the receive signaling registers, the DS21455/DS21458 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1 through RSCSE4 for E1 and RSCSE1 through RSCSE3 for T1 are used to select which channels can cause a change of state indication ...
Page 95
... When the error condition subsides, the signaling data will be held in the old state for at least an additional 9ms (or 4.5ms in D4 framing mode) before being allowed to be updated with new signaling data. DS21455/DS21458 Quad T1/E1/J1 Transceivers 95 of 269 ...
Page 96
... Bit 6/Unused, must be set to zero for proper operation. Bit 7/Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reinsert all signaling channels without programming all channels through the per-channel function not reinsert all signaling 1 = reinsert all signaling DS21455/DS21458 Quad T1/E1/J1 Transceivers — ...
Page 97
... CH13-A CH13-B CH14-B CH15-A CH15-B CH16-B CH17-A CH17-B CH18-B CH19-A CH19-B CH20-B CH21-A CH21-B CH22-B CH23-A CH23-B CH24 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers (LSB) CH1-C CH1-D RS1 CH3-C CH3-D RS2 CH5-C CH5-D RS3 CH7-C CH7-D RS4 CH9-C CH9-D RS5 CH11-C CH11-D ...
Page 98
... DS21455/DS21458 Quad T1/E1/J1 Transceivers (LSB RS1 CH1-C CH1-D RS2 CH3-C CH3-D RS3 CH5-C CH5-D RS4 CH7-C CH7-D RS5 CH9-C CH9-D RS6 CH11-C CH11-D ...
Page 99
... CH21 CH20 CH19 CH29 CH28 CH27 CH5 CH4 CH3 CH13 CH12 CH11 CH21 CH20 CH19 CH29 CH28 CH27 99 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers (LSB) CH2 CH1 RSCSE1 CH10 CH9 RSCSE2 CH18 CH17 RSCSE3 CH26 CH25 RSCSE4 (LSB) CH2 CH1 RSINFO1 CH10 ...
Page 100
... T1TCR1.4 (T1 Mode) or E1TCR1.6 (E1 Mode mode, only TS1 through TS12 are used. Signaling data can be sourced from the TS registers on a per-channel basis by utilizing the software- signaling insertion-enable registers, SSIE1 through SSIE4. DS21455/DS21458 Quad T1/E1/J1 Transceivers TRANSMIT SIGNALING REGISTERS ...
Page 101
... Channel Phone Channel DS21455/DS21458 Quad T1/E1/J1 Transceivers 101 of 269 ...
Page 102
... DS21455/DS21458 Quad T1/E1/J1 Transceivers (LSB TS1 CH1-C CH1-D TS2 CH3-C CH3-D TS3 CH5-C CH5-D TS4 CH7-C CH7-D TS5 CH9-C CH9-D TS6 CH11-C CH11-D ...
Page 103
... CH13-A CH13-B CH14-B CH15-A CH15-B CH16-B CH17-A CH17-B CH18-B CH19-A CH19-B CH20-B CH21-A CH21-B CH22-B CH23-A CH23-B CH24-B 103 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers (LSB) CH1-C CH1-D TS1 CH3-C CH3-D TS2 CH5-C CH5-D TS3 CH7-C CH7-D TS4 CH9-C CH9-D TS5 CH11-C CH11-D ...
Page 104
... Bits 0 to 7/Software Signaling Insertion Enable for Channels (CH8 to CH15). These bits determine which channels are to have signaling inserted form the transmit signaling registers not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 105
... Bits 0 to 7/Software Signaling Insertion Enable for Channels (CH23 to CH30). These bits determine which channels are to have signaling inserted form the transmit signaling registers not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 106
... Bits 0 to 7/Software Signaling Insertion Enable for and Channels (CH17 to CH24). These bits determine what channels are to have signaling inserted form the transmit signaling registers not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 107
... TSIG pin inserted into them on a per- channel basis. See the Special Per-Channel Operation section. The signaling insertion capabilities of the framer are available whether the transmit-side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz. DS21455/DS21458 Quad T1/E1/J1 Transceivers 107 of 269 ...
Page 108
... When operated in the T1 mode, only the first 24 channels are used; the remaining channels, CH25–CH32 are not used. The DS21455/DS21458 contain a 64-byte idle code array accessed by the idle array address register (IAAR) and the per-channel idle code register (PCICR). The contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels. This substitution can be enabled and disabled on a per-channel basis by the transmit-channel idle-code enable registers (TCICE1– ...
Page 109
... Write RCICE2 = FFh ;enable idle code substitution for receive channels 9 through 16 Write RCICE3 = FEh ;enable idle code substitution for receive channels 18 through 24 Write RCICE4 = FFh ;enable idle code substitution for receive channels 25 through 32 DS21455/DS21458 Quad T1/E1/J1 Transceivers 109 of 269 ...
Page 110
... Bits 0 to 7/Transmit Channels Code Insertion Control Bits (CH9 to CH16 not insert data from the idle code array into the transmit data stream 1 = insert data from the idle code array into the transmit data stream DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 111
... Bits 0 to 7/Receive Channels Code Insertion Control Bits (CH9 to CH16 not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 112
... Bits 0 to 7/Receive Channels Code Insertion Control Bits (CH25 to CH32 not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 113
... TCHBLK pin will be held high during the entire corresponding channel time. Channels 25 through 32 are ignored when the device is operated in the T1 mode. Also, the DS21455/DS21458 can internally generate and output a bursty clock on a per-channel basis (N x 64kbps / 56kbps). See the Fractional T1/E1 Support section. ...
Page 114
... CH15 Default 0 0 Bits 0 to 7/Transmit Channels Channel Blocking Control Bits (CH9 to CH16 force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time DS21455/DS21458 Quad T1/E1/J1 Transceivers CH22 CH21 CH20 CH19 ...
Page 115
... CH31 Default 0 0 Bits 0 to 7/Transmit Channels Channel Blocking Control Bits (CH25 to CH32 force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time DS21455/DS21458 Quad T1/E1/J1 Transceivers CH22 CH21 CH20 CH19 ...
Page 116
... ELASTIC STORES OPERATION The DS21455/DS21458 contain dual two-frame, fully independent elastic stores, one for the receive direction and one for the transmit direction. The transmit- and receive-side elastic stores can be enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or 2 ...
Page 117
... If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See the Elastic Stores Initialization section for details. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 118
... Bit 3/Transmit Elastic Store Slip Occurrence Event (TSLIP interrupt masked 1 = interrupt enabled Bit 4/Transmit Elastic Store Empty Event (TESEM interrupt masked 1 = interrupt enabled Bit 5/Transmit Elastic Store Full Event (TESF interrupt masked 1 = interrupt enabled DS21455/DS21458 Quad T1/E1/J1 Transceivers TESF TESEM TSLIP RESF 0 ...
Page 119
... If the buffer empties, then a full frame of data will be repeated at RSER and the SR5.0 and SR5.1 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the SR5.0 and SR5.2 bits will be set to a one. DS21455/DS21458 Quad T1/E1/J1 Transceivers 119 of 269 ...
Page 120
... RCLK/TCLK, respectively). See Table 20-1. Elastic Store Delay After Initialization INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align DS21455/DS21458 Quad T1/E1/J1 Transceivers Table 20-1 for details. REGISTER BIT ESCR.2 8 Clocks < Delay < 1 Frame ESCR.6 1 Frame < ...
Page 121
... On power-up, after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bits (ESCR.2 and ESCR.6) should be toggled from a zero to a one to ensure proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers 121 of 269 ...
Page 122
... G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS21455/DS21458 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions ...
Page 123
... T1 BIT ORIENTED CODE (BOC) CONTROLLER The DS21455/DS21458 contain a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 22.1 Transmit BOC Bits 0 through 5 in the TFDL register contain the BOC message to be transmitted. Setting BOCC causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position ...
Page 124
... BOC function disabled 1 = receive BOC function enabled. The RFDL register will report BOC messages Bit 5/Unused, must be set to zero for proper operation. Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers — ...
Page 125
... Bit 3/RFDL Register Full Event (RFDLF). Set when the receive FDL buffer (RFDL) fills to capacity. Bit 4/RFDL Abort Detect Event (RFDLAD). Set when eight consecutive ones are received on the FDL. Bit 5/BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 126
... Bit 3/RFDL Register Full Event (RFDLF interrupt masked 1 = interrupt enabled Bit 4/RFDL Abort Detect Event (RFDLAD interrupt masked 1 = interrupt enabled Bit 5/BOC Clear Event (BOCC interrupt masked 1 = interrupt enabled DS21455/DS21458 Quad T1/E1/J1 Transceivers BOCC RFDLAD RFDLF TFDLE ...
Page 127
... ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) The DS21455/DS21458, when operated in the E1 mode, provide for access to both the Sa and the Si bits via three different methods. The first method is via a hardware scheme using the RLINK/RLCLK and TLINK/TLCLK pins. The second method involves using the internal RAF/RNAF and TAF/TNAF registers ...
Page 128
... Default 0 0 Bit 0/Additional Bit 8 (Sa8). Bit 1/Additional Bit 7 (Sa7). Bit 2/Additional Bit 6 (Sa6). Bit 3/Additional Bit 5 (Sa5). Bit 4/Additional Bit 4 (Sa4). Bit 5 / Remote Alarm (A). Bit 6/Frame Nonalignment Signal Bit (1). Bit 7/International Bit (Si). DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 129
... Bit 0/Additional Bit 8 (Sa8). Bit 1/Additional Bit 7 (Sa7). Bit 2/Additional Bit 6 (Sa6). Bit 3/Additional Bit 5 (Sa5). Bit 4/Additional Bit 4 (Sa4). Bit 5/Remote Alarm (used to transmit the alarm A). Bit 6/Frame Nonalignment Signal Bit (1). Bit 7/International Bit (Si). DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 130
... Bit 0/Si Bit of Frame 14(SiF14). Bit 1/Si Bit of Frame 12(SiF12). Bit 2/Si Bit of Frame 10(SiF10). Bit 3/Si Bit of Frame 8(SiF8). Bit 4/Si Bit of Frame 6(SiF6). Bit 5/Si Bit of Frame 4(SiF4). Bit 6/Si Bit of Frame 2(SiF2). Bit 7/Si Bit of Frame 0(SiF0). DS21455/DS21458 Quad T1/E1/J1 Transceivers SiF4 SiF6 SiF8 SiF10 0 0 ...
Page 131
... Bit 2/Remote Alarm Bit of Frame 11(RRAF11). Bit 3/Remote Alarm Bit of Frame 9(RRAF9). Bit 4/Remote Alarm Bit of Frame 7(RRAF7). Bit 5/Remote Alarm Bit of Frame 5(RRAF5). Bit 6/Remote Alarm Bit of Frame 3(RRAF3). Bit 7/Remote Alarm Bit of Frame 1(RRAF1). DS21455/DS21458 Quad T1/E1/J1 Transceivers SiF5 SiF7 ...
Page 132
... Bit 1/Sa5 Bit of Frame 13(RSa5F13). Bit 2/Sa5 Bit of Frame 11(RSa5F11). Bit 3/Sa5 Bit of Frame 9(RSa5F9). Bit 4/Sa5 Bit of Frame 7(RSa5F7). Bit 5/Sa5 Bit of Frame 5(RSa5F5). Bit 6/Sa5 Bit of Frame 3(RSa5F3). Bit 7/Sa5 Bit of Frame 1(RSa5F1). DS21455/DS21458 Quad T1/E1/J1 Transceivers RSa4F5 RSa4F7 RSa4F9 ...
Page 133
... Bit 1/Sa7 Bit of Frame 13(RSa7F13). Bit 2/Sa7 Bit of Frame 11(RSa7F11). Bit 3/Sa7 Bit of Frame 9(RSa7F9). Bit 4/Sa7 Bit of Frame 7(RSa7F7). Bit 5/Sa7 Bit of Frame 5(RSa7F5). Bit 6/Sa7 Bit of Frame 3(RSa7F3). Bit 7/Sa7 Bit of Frame 1(RSa4F1). DS21455/DS21458 Quad T1/E1/J1 Transceivers RSa6F5 RSa6F7 RSa6F9 ...
Page 134
... Bit 1/Sa8 Bit of Frame 13(RSa8F13). Bit 2/Sa8 Bit of Frame 11(RSa8F11). Bit 3/Sa8 Bit of Frame 9(RSa8F9). Bit 4/Sa8 Bit of Frame 7(RSa8F7). Bit 5/Sa8 Bit of Frame 5(RSa8F5). Bit 6/Sa8 Bit of Frame 3(RSa8F3). Bit 7/Sa8 Bit of Frame 1(RSa8F1). DS21455/DS21458 Quad T1/E1/J1 Transceivers RSa8F5 RSa8F7 RSa8F9 ...
Page 135
... Bit 0/Si Bit of Frame 14(TsiF14). Bit 1/Si Bit of Frame 12(TsiF12). Bit 2/Si Bit of Frame 10(TsiF10). Bit 3/Si Bit of Frame 8(TsiF8). Bit 4/Si Bit of Frame 6(TsiF6). Bit 5/Si Bit of Frame 4(TsiF4). Bit 6/Si Bit of Frame 2(TsiF2). Bit 7/Si Bit of Frame 0(TsiF0). DS21455/DS21458 Quad T1/E1/J1 Transceivers TsiF4 TsiF6 TsiF8 TsiF10 0 0 ...
Page 136
... Bit 2/Remote Alarm Bit of Frame 11(TRAF11). Bit 3/Remote Alarm Bit of Frame 9(TRAF9). Bit 4/Remote Alarm Bit of Frame 7(TRAF7). Bit 5/Remote Alarm Bit of Frame 5(TRAF5). Bit 6/Remote Alarm Bit of Frame 3(TRAF3). Bit 7/Remote Alarm Bit of Frame 1(TRAF1). DS21455/DS21458 Quad T1/E1/J1 Transceivers TsiF5 TsiF7 ...
Page 137
... Bit 1/Sa5 Bit of Frame 13(TSa5F13). Bit 2/Sa5 Bit of Frame 11(TSa5F11). Bit 3/Sa5 Bit of Frame 9(TSa5F9). Bit 4/Sa5 Bit of Frame 7(TSa5F7). Bit 5/Sa5 Bit of Frame 5(TSa5F5). Bit 6/Sa5 Bit of Frame 3(TSa5F3). Bit 7/Sa5 Bit of Frame 1(TSa5F1). DS21455/DS21458 Quad T1/E1/J1 Transceivers TSa4F5 TSa4F7 TSa4F9 ...
Page 138
... Bit 1/Sa7 Bit of Frame 13(TSa7F13). Bit 2/Sa7 Bit of Frame 11(TSa7F11). Bit 3/Sa7 Bit of Frame 9(TSa7F9). Bit 4/Sa7 Bit of Frame 7(TSa7F7). Bit 5/Sa7 Bit of Frame 5(TSa7F5). Bit 6/Sa7 Bit of Frame 3(TSa7F3). Bit 7/Sa7 Bit of Frame 1(TSa4F1). DS21455/DS21458 Quad T1/E1/J1 Transceivers TSa6F5 TSa6F7 TSa6F9 ...
Page 139
... Bit 1/Sa8 Bit of Frame 13(TSa8F13). Bit 2/Sa8 Bit of Frame 11(TSa8F11). Bit 3/Sa8 Bit of Frame 9(TSa8F9). Bit 4/Sa8 Bit of Frame 7(TSa8F7). Bit 5/Sa8 Bit of Frame 5(TSa8F5). Bit 6/Sa8 Bit of Frame 3(TSa8F3). Bit 7/Sa8 Bit of Frame 1(TSa8F1). DS21455/DS21458 Quad T1/E1/J1 Transceivers TSa8F5 TSa8F7 TSa8F9 ...
Page 140
... TSiNAF register into the transmit data stream Bit 7/International Bit in Align Frame Insertion Control Bit (SiAF not insert data from the TSiAF register into the transmit data stream 1 = insert data from the TSiAF register into the transmit data stream DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 141
... To allow the framer to properly source/receive data from/to the HDLC controllers, the legacy FDL circuitry (See the Legacy FDL Support (T1 Mode) section.) should be disabled. The HDLC registers are divided into four groups: control/configuration, status/information, mapping, and FIFOs. Table 24-1 lists these registers by group. DS21455/DS21458 Quad T1/E1/J1 Transceivers 141 of 269 ...
Page 142
... H1RF, HDLC #1 Receive FIFO Register H2RF, HDLC #2 Receive FIFO Register H1TF, HDLC #1 Transmit FIFO Register H2TF, HDLC #2 Transmit FIFO Register DS21455/DS21458 Quad T1/E1/J1 Transceivers CONTROL/CONFIGURATION General control over the transmit HDLC controllers General control over the receive HDLC controllers Sets high watermark for receiver and low watermark for ...
Page 143
... CRC code to the end of all messages. This is useful for transmitting consecutive SS7 FISUs without host intervention. Bit 7/Number Of Flags Select (NOFS send one flag between consecutive messages 1 = send two flags between consecutive messages DS21455/DS21458 Quad T1/E1/J1 Transceivers THR ...
Page 144
... HDLC assigned to FDL (T1 mode), Sa Bits (E1 mode) Bit 7/Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Must be cleared and set again for a subsequent reset normal operation 1 = reset receive HDLC controller and flush the receive FIFO DS21455/DS21458 Quad T1/E1/J1 Transceivers — ...
Page 145
... Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers TFLWM2 TFLWM1 TFLWM0 RECEIVE FIFO WATERMARK (BYTES) TRANSMIT FIFO WATERMARK (BYTES) 145 of 269 2 1 RFHWM2 ...
Page 146
... Bit 4/Receive HDLC Channel Select Bit 4 (RHCS4). Select Channel 5, 13, 21, or 29. Bit 5/Receive HDLC Channel Select Bit 5 (RHCS5). Select Channel 6, 14, 22, or 30. Bit 6/Receive HDLC Channel Select Bit 6 (RHCS6). Select Channel 7, 15, 23, or 31. Bit 7/Receive HDLC Channel Select Bit 7 (RHCS7). Select Channel 8, 16, 24, or 32. DS21455/DS21458 Quad T1/E1/J1 Transceivers CHANNELS 5 4 ...
Page 147
... Bit 6/Receive Channel Bit 7 Suppress Enable (RCB7SE). Set to one to stop this bit from being used. Bit 7/Receive Channel Bit 8 Suppress Enable (RCB8SE). MSB of the channel. Set to one to stop this bit from being used RCB6SE RCB5SE RCB4SE 147 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers RCB3SE RCB2SE RCB1SE ...
Page 148
... Bit 4/Transmit HDLC Channel Select Bit 4 (THCS4). Select Channel 5, 13, 21, or 29. Bit 5/Transmit HDLC Channel Select Bit 5 (THCS5). Select Channel 6, 14, 22, or 30. Bit 6/Transmit HDLC Channel Select Bit 6 (THCS6). Select Channel 7, 15, 23, or 31. Bit 7/Transmit HDLC Channel Select Bit 7 (THCS7). Select Channel 8, 16, 24, or 32. DS21455/DS21458 Quad T1/E1/J1 Transceivers CHANNELS 5 4 ...
Page 149
... Bit 6/Transmit Channel Bit 7 Suppress Enable (TCB1SE). Set to one to stop this bit from being used. Bit 7/Transmit Channel Bit 8 Suppress Enable (TCB1SE). MSB of the channel. Set to one to stop this bit from being used TCB6SE TCB5SE TCB4SE 149 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers TCB3SE TCB2SE TCB1SE ...
Page 150
... This is a latched bit and will be cleared when read. Bit 6/Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. This is a latched bit and will be cleared when read. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 151
... Bit 4/Receive Packet Start Event (RPS interrupt masked 1 = interrupt enabled Bit 5/Receive Packet End Event (RPE interrupt masked 1 = interrupt enabled Bit 6/Transmit Message End Event (TMEND interrupt masked 1 = interrupt enabled DS21455/DS21458 Quad T1/E1/J1 Transceivers RPE RPS RHWM RNE 0 0 ...
Page 152
... Bit 2/HDLC #2 Opening Byte Event (H2OBT). Set when the next byte available in the receive FIFO is the first byte of a message. Bit 3/HDLC #2 Transmit FIFO Underrun Event (H2UDR). Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. This bit is latched and will be cleared when read. DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 153
... RPBA0 through RPBA6 are the end of a message. Host must check the INFO5 or INFO6 register for details bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the INFO5 or INFO6 register. DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 154
... Bit 3/Receive HDLC Data Bit 3 (RHD3). Bit 4/Receive HDLC Data Bit 4 (RHD4). Bit 5/Receive HDLC Data Bit 5 (RHD5). Bit 6/Receive HDLC Data Bit 6 (RHD6). Bit 7/Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte. DS21455/DS21458 Quad T1/E1/J1 Transceivers THD5 ...
Page 155
... If the zero destuffer sees six or more ones in a row followed by a zero, the zero is not removed. The T1RCR2.3 bit should always be set to a one when the device is extracting the FDL. More on how to use the DS21455/DS21458 in FDL applications in this legacy support mode is covered in a separate application note. ...
Page 156
... Bit 3/Receive FDL Match Bit 3 (RFDLM3). Bit 4/Receive FDL Match Bit 4 (RFDLM4). Bit 5/Receive FDL Match Bit 5 (RFDLM5). Bit 6/Receive FDL Match Bit 6 (RFDLM6). Bit 7/Receive FDL Match Bit 7 (RFDLM7). MSB of the FDL Match Code. DS21455/DS21458 Quad T1/E1/J1 Transceivers RFDL5 RFDL4 ...
Page 157
... TFDL register) T1TCR2 (allow the TFDL register to load on multiframe boundaries). Since the SLC-96 message fields share the Fs-bit position, the user can access these message fields via the TFDL and RFDL registers. Please see the separate application note for a detailed description of how to implement a SLC-96 function. DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 158
... LINE INTERFACE UNIT (LIU) The LIU in the DS21455/DS21458 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which wave-shapes and drives the network line; and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described below ...
Page 159
... Data input at TPOSI and TNEGI is sent via the jitter attenuation MUX to the wave shaping circuitry and line driver. The DS21455/DS21458 will drive the line from the TTIP and TRING pins via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1 ...
Page 160
... When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition will occur and the RCLK will be derived from the JACLK source. 25.2.1 Receive Level Indicator The DS21455/DS21458 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3- RL0 located in the Information Register 2 (INFO2). This feature is helpful when trouble shooting line performance problems. ...
Page 161
... TRING pins. 25.3.2 Transmit Open-Circuit Detector The DS21455/DS21458 can also detect when the TTIP or TRING outputs are open circuited. TOCD (INFO2.4) will provide a real-time indication of when an open circuit is detected. SR1 provides a latched version of the information (SR1.1), which can be used to activate an interrupt when enable via the IMR1 register ...
Page 162
... T1 applications. Setting JAMUX (LIC2. logic 0 bypasses this PLL. 25.5 Jitter Attenuator The DS21455/DS21458 contain an on-board jitter attenuator that can be set to a depth of either 32 bits or 128 bits via the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected ...
Page 163
... CMI (Code Mark Inversion) Option The DS21455/DS21458 provide a CMI interface for connection to optical transports. This interface is a unipolar 1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration of the clock period. Zeros are encoded as a zero-to-one transition at the middle of the clock period. ...
Page 164
... Using TT0 and TT1 of the LICR4 register, users can then select the proper internal source termination. Line build-outs 100 and 101 are provided for backward compatibility with older products only. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 165
... DSX-1 (133 to 266 feet) DSX-1 (266 to 399 feet) DSX-1 (399 to 533 feet) DSX-1 (533 to 655 feet) -7.5dB CSU -15dB CSU -22.5dB CSU * TT0 and TT1 of the LIC4 register must be set to zero in this configuration . **N.M. = not meaningful. DS21455/DS21458 Quad T1/E1/J1 Transceivers LIC1.7 LIC1.6 LIC1.5 PSA1 (L2) (L1) (L0) (F1h) 0 ...
Page 166
... Bit 6/Automatic Gain Control Disable (AGCD use Transmit AGC, TLBC bits 0–5 are “don’t care” not use Transmit AGC, TLBC bits 0–5 set nominal level Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers GC5 ...
Page 167
... Bit 6/Line Interface Reset (LIRST). Setting this bit from a zero to a one will initiate an internal reset that resets the clock recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Bit 7/E1/T1 Select (ETS Mode Selected Mode Selected DS21455/DS21458 Quad T1/E1/J1 Transceivers IBPV TUA1 ...
Page 168
... Bit 6/Transmit Clock Edge Select (TCES). Selects which TCLKI edge to sample TPOSI and TNEGI sample TPOSI and TNEGI on falling edge of TCLKI 1 = sample TPOSI and TNEGI on rising edge of TCLKI Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers RCES ...
Page 169
... Bit 6/CMI Invert (CMII CMI normal at TTIP and RTIP 1 = invert CMI signal at TTIP and RTIP Bit 7/CMI Enable (CMIE disable CMI mode 1 = enable CMI mode DS21455/DS21458 Quad T1/E1/J1 Transceivers MPS1 MPS0 TT1 JAMUX (LIC2. ...
Page 170
... Bit 7/BERT Real-Time Synchronization Status (BSYNC). Real-time status of the synchronizer (this bit is not latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will be cleared when six or more bits out of 64 are received in error. Refer to BSYNC in the BERT status register, SR9, for an interrupt-generating version of this signal. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 171
... Bit 7/Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls below the threshold set by the value in CCR4.4 through CCR4.7. The level must remain below the programmed threshold for approximately 50ms for this bit to be set. This is a double interrupt bit (See Section 8.3). DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 172
... Bit 5/Receive Signaling Change-of-State Event (RSCOS interrupt masked 1 = interrupt enabled Bit 6/Timer Event (TIMER interrupt masked 1 = interrupt enabled Bit 7/Input Level Under Threshold (ILUT interrupt masked 1 = interrupt enabled DS21455/DS21458 Quad T1/E1/J1 Transceivers RSCOS JALT LRCL 172 of 269 ...
Page 173
... The area under this portion of the circuit should not contain power planes. Some T1 (never in E1) applications source or sink power from the network-side center taps of Note 3: the Rx/Tx transformers. A list of transformer part numbers and manufacturers is available by contacting Note 4: telecom.support@dalsemi.com. DS21455/DS21458 Quad T1/E1/J1 Transceivers 1.0 2:1 T2 ...
Page 174
... Some T1 (never in E1) applications source or sink power from the network-side center taps of Note 4: the Rx/Tx transformers. The ground trace connected to the S2/S3 pair and the S4/S5 pair should be at least 50 mils wide Note 5: to conduct the extra current from a longitudinal power-cross event. DS21455/DS21458 Quad T1/E1/J1 Transceivers 1.0 ...
Page 175
... Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary DS21455/DS21458 Quad T1/E1/J1 Transceivers RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) ±2% 600H minimum 1.0H maximum 40pF maximum 1.0Ω maximum 2.0Ω maximum 1.2Ω maximum 1.2Ω ...
Page 176
... Figure 25-7. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 Figure 25-8. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -500 DS21455/DS21458 Quad T1/E1/J1 Transceivers 194ns 219ns -200 -150 -100 - TIME (ns) MAXIMUM CURVE UI -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 T1.102/87, T1.403, CB 119 (Oct. 79), & I.431 Template -400 -300 -200 -100 0 100 200 300 TIME (ns) 176 of 269 269ns G.703 ...
Page 177
... Figure 25-9. Jitter Tolerance 1K 100 10 1 0.1 1 Figure 25-10. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 DS21455/DS21458 Quad T1/E1/J1 Transceivers DS21458 /455 Tolerance TR 62411 (Dec. 90) ITU-T G.823 10 100 1K FREQUENCY (Hz) DS21458/455 T1 MODE 10 100 1K FREQUENCY (Hz) 177 of 269 10K 100K TR 62411 (Dec. 90) Prohibited Area 10K 100K ...
Page 178
... Figure 25-11. Jitter Attenuation (E1 Mode) 0dB -20dB -40dB -60dB 1 DS21455/DS21458 Quad T1/E1/J1 Transceivers TBR12 Prohibited Area DS21458/455 E1 MODE 10 100 1K FREQUENCY (Hz) 178 of 269 ITU G.7XX Prohibited Area 10K 100K ...
Page 179
... PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS21455/DS21458 can generate and detect a repeating bit pattern from 1 bit to 8 bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user will load the pattern to be sent into the transmit code definition registers (TCD1 and TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code-control (IBCC) register ...
Page 180
... Bits 6 to 7/Transmit Code Length Definition Bits (TC0 to TC1). TC1 TC0 LENGTH SELECTED (Bits DS21455/DS21458 Quad T1/E1/J1 Transceivers RUP2 RUP1 RUP0 RDN2 LENGTH SELECTED (Bits 8/16 LENGTH SELECTED (Bits) 1 ...
Page 181
... Bit 5/Transmit Code Definition Bit 5 (C5). A “don’t care” 5-, 6-, or 7-bit length is selected. Bit 6/Transmit Code Definition Bit 6 (C6). A “don’t care” 5-, 6-, or 7-bit length is selected. Bit 7/Transmit Code Definition Bit 7 (C7). A “don’t care” 5-, 6-, or 7-bit length is selected. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 182
... Bit 5/Receive-Up Code Definition Bit 5 (C5). A “don’t care” 1-bit to 7-bit length is selected. Bit 6/Receive-Up Code Definition Bit 6 (C6). A “don’t care” 1-bit to 7-bit length is selected. Bit 7/Receive-Up Code Definition Bit 7 (C7). A “don’t care” 1-bit to 7-bit length is selected. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 183
... Bit 5/Receive-Down Code Definition Bit 5 (C5). A “don’t care” 1-bit or 2-bit length is selected. Bit 6/Receive-Down Code Definition Bit 6 (C6). A “don’t care” 1-bit length is selected. Bit 7/Receive-Down Code Definition Bit 7 (C7). First bit of the repeating pattern. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 184
... Bit 3/Unused, must be set to zero for proper operation. Bit 4/Unused, must be set to zero for proper operation. Bit 5/Unused, must be set to zero for proper operation. Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers ...
Page 185
... Bit 5/Receive-Spare Code Definition Bit 5 (C5). A “don’t care” 1-bit to 7-bit length is selected. Bit 6/Receive-Spare Code Definition Bit 6 (C6). A “don’t care” 1-bit to 7-bit length is selected. Bit 7/Receive-Spare Code Definition Bit 7 (C7). A “don’t care” 1-bit to 7-bit length is selected. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 186
... BERT via this register. A major change of state is defined as either a change in the receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected overflow has occurred in either the bit counter or the error counter. The host must read SR9 to determine the change of state. DS21455/DS21458 Quad T1/E1/J1 Transceivers SS 186 of 269 ...
Page 187
... Bit 7/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for a subsequent loads. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 188
... EIB0 SBE RPL3 RPL1 RPL0 188 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers RPL2 RPL1 RPL0 ...
Page 189
... Bit 5/Unused, must be set to zero for proper operation. Bit 6/Receive Framed/Unframed Select (RFUS). For T1 mode only BERT will not sample data from the F-bit position (framed BERT will sample data from the F-bit position (unframed) Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers — ...
Page 190
... Cleared when read and will not be set again until another overflow occurs. Bit 6/BERT Bit Error Detected (BED) Event (BBED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it detect bit errors. Cleared when read. DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 4 ...
Page 191
... Bits 0 to 7/Alternating Word Count Rate Bits (ACNT0 to ACNT7). ACNT0 is the LSB of the 8-bit alternating word count rate counter BBCO BEC0 BRA1 ACNT5 ACNT4 ACNT3 191 of 269 DS21455/DS21458 Quad T1/E1/J1 Transceivers BRA0 BRLOS BSYNC ACNT2 ACNT1 ACNT0 ...
Page 192
... BERT Repetitive Pattern Set Register 4 Register Address: DFh Bit # 7 6 Name RPAT31 RPAT30 Default 0 0 Bits 0 to 7/BERT Repetitive Pattern Set Bits (RPAT24 to RPAT31). RPAT31 is the LSB of the 32-bit repetitive pattern set. DS21455/DS21458 Quad T1/E1/J1 Transceivers RPAT5 RPAT4 RPAT3 RPAT13 ...
Page 193
... Register Description: BERT Bit Count Register 4 Register Address: E6h Bit # 7 6 Name BBC31 BBC30 Default 0 0 Bits 0 to 7/BERT Bit Counter Bits (BBC24 to BBC31). BBC31 is the MSB of the 32-bit counter. DS21455/DS21458 Quad T1/E1/J1 Transceivers BBC5 BBC4 BBC3 BBC13 ...
Page 194
... Register Description: BERT Error Count Register 3 Register Address: E9h Bit # 7 6 Name EC23 EC22 Default 0 0 Bits 0 to 7/Error Counter Bits (EC16 to EC23). EC23 is the MSB of the 24-bit counter. DS21455/DS21458 Quad T1/E1/J1 Transceivers EC5 EC4 EC3 EC13 ...
Page 195
... PAYLOAD ERROR INSERTION FUNCTION An error-insertion function is available in the DS21455/DS21458 and is used to create errors in the payload portion of the T1 frame in the transmit path. Errors can be inserted over the entire frame per-channel basis. The user can select all DS0s or any combination of DS0s. See the Special Per-Channel Registration Operation section for information on using the per-channel function ...
Page 196
... NOEx registers. The toggling of this bit causes the error count loaded into the NOEx registers to be loaded into the error insertion circuitry on the next clock cycle. Subsequent updates require that the WNOE bit be set to zero and then one once again. DS21455/DS21458 Quad T1/E1/J1 Transceivers — ...
Page 197
... Default 0 0 Bits 0 to 1/Number of Errors Counter Bits (C8 to C9). Bit C9 is the MSB of the 10-bit counter. DS21455/DS21458 Quad T1/E1/J1 Transceivers READ No errors left to be inserted One error left to be inserted Two errors left to be inserted 1023 errors left to be inserted ...
Page 198
... Register Description: Number Of Errors Left 2 Register Address: EFh Bit # 7 6 Name — — Default 0 0 Bits 0 to 1/Number of Errors Left Counter Bits (C8 to C9). Bit C9 is the MSB of the 10-bit counter. DS21455/DS21458 Quad T1/E1/J1 Transceivers — ...
Page 199
... In channel interleave mode, data is output to the PCM data-out bus one channel at a time from each of the connected devices until all channels of frame n from each device has been placed on the bus. This mode can be used even when the DS21455/DS21458s are operating asynchronous to each other. The elastic stores will manage slip conditions. ...
Page 200
... IBS0 BUS SIZE 0 0 Two Devices on Bus 0 1 Four Devices on Bus 1 0 Eight Devices on Bus 1 1 Reserved for Future Use Bit 7/Unused, must be set to zero for proper operation. DS21455/DS21458 Quad T1/E1/J1 Transceivers IBS0 IBOSEL IBOEN 200 of 269 DA2 DA1 ...