DS21458-W+ Maxim Integrated, DS21458-W+ Datasheet - Page 44

• Manufacturer Part Number: DS21458-W+
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS21458-W+

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CSBGA
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 3.3 V
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Part # Aliases: 90-21458+W00

ADDRESS
AA
AB
AC
AD
BA
BD
AE
AF
BB
BC
BE
9A
9B
9C
9D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
9E
9F
94
95
96
97
98
99
HDLC #1 Receive Channel Select 3
HDLC #1 Receive Channel Select 4
HDLC #1 Receive Time Slot Bits/Sa Bits Select
HDLC #1 Transmit Channel Select1
HDLC #1 Transmit Channel Select 2
HDLC #1 Transmit Channel Select 3
HDLC #1 Transmit Channel Select 4
HDLC #1 Transmit Time Slot Bits/Sa Bits Select
HDLC #1 Receive Packet Bytes Available
HDLC #1 Transmit FIFO
HDLC #1 Receive FIFO
HDLC #1 Transmit FIFO Buffer Available
HDLC #2 Transmit Control
HDLC #2 FIFO Control
HDLC #2 Receive Channel Select 1
HDLC #2 Receive Channel Select 2
HDLC #2 Receive Channel Select 3
HDLC #2 Receive Channel Select 4
HDLC #2 Receive Time Slot Bits/Sa Bits Select
HDLC #2 Transmit Channel Select 1
HDLC #2 Transmit Channel Select 2
HDLC #2 Transmit Channel Select 3
HDLC #2 Transmit Channel Select 4
HDLC #2 Transmit Time Slot Bits/Sa Bits Select
HDLC #2 Receive Packet Bytes Available
HDLC #2 Transmit FIFO
HDLC #2 Receive FIFO
HDLC #2 Transmit FIFO Buffer Available
Extend System Information Bus Control Register 1
Extend System Information Bus Control Register 2
Extend System Information Bus Register 1
Extend System Information Bus Register 2
Extend System Information Bus Register 3
Extend System Information Bus Register 4
In-Band Code Control Register
Transmit Code Definition Register 1
Transmit Code Definition Register 2
Receive Up Code Definition Register 1
Receive Up Code Definition Register 2
Receive Down Code Definition Register 1
Receive Down Code Definition Register 2
In-Band Receive Spare Control Register
Receive Spare Code Definition Register 1
Receive Spare Code Definition Register 2
Receive FDL Register
Transmit FDL Register
Receive FDL Match Register 1
Receive FDL Match Register 2
Unused. Must be set = 00h for proper operation
Interleave Bus Operation Control Register
Receive Align Frame Register
Receive Nonalign Frame Register
Receive Si Align Frame
REGISTER NAME
44 of 269
DS21455/DS21458 Quad T1/E1/J1 Transceivers
ABBREVIATION
REGISTER
H1RTSBS
H2RTSBS
H1TTSBS
H2TTSBS
ESIBCR1
ESIBCR2
RDNCD1
RDNCD2
RFDLM1
RFDLM2
H1RPBA
H1TFBA
H2RPBA
H2TFBA
RUPCD1
RUPCD2
H1RCS3
H1RCS4
H1TCS1
H1TCS2
H1TCS3
H1TCS4
H2RCS1
H2RCS2
H2RCS3
H2RCS4
H2TCS1
H2TCS2
H2TCS3
H2TCS4
RSCD1
RSCD2
RSiAF
ESIB1
ESIB2
ESIB3
ESIB4
RNAF
H2TC
RSCC
RFDL
TFDL
H1TF
H1RF
H2FC
H2TF
H2RF
TCD1
TCD2
IBOC
IBCC
RAF
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