DS21458-W+ Maxim Integrated, DS21458-W+ Datasheet - Page 209

• Manufacturer Part Number: DS21458-W+
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS21458-W+

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CSBGA
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 3.3 V
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Part # Aliases: 90-21458+W00

32. FRACTIONAL T1/E1 SUPPORT
The DS21455/DS21458 can be programmed to output gapped clocks for selected channels in the receive
and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or
ISDN-PRI applications. This is accomplished by assigning an alternate function to the RCHCLK and
TCHCLK pins. When the gapped clock feature is enabled, a gated clock is output on the RCHCLK and/or
TCHCLK pins. The channel selection is controlled via the special per-channel control registers. No clock
is generated at the F-bit position. The receive and transmit paths have independent enables. Channel
formats supported include 56kbps and 64kbps.
When 56kbps mode is selected, the clock corresponding to the data/control bit in the channel is omitted.
Only the seven most significant bits of the channel have clocks.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Gapped-Clock Enable (RGPCKEN).
Bit 1/Receive Channel-Data Format (RDATFMT).
Bit 2/Transmit Gapped-Clock Enable (TGPCKEN).
Bit 3/Transmit Channel-Data Format (TDATFMT).
Bit 4/Unused, must be set to zero for proper operation.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.
0 = RCHCLK functions normally
1 = enable gapped-bit clock output on RCHCLK
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in 7 out of the 8 bits)
0 = TCHCLK functions normally
1 = enable gapped-bit clock output on TCHCLK
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in 7 out of the 8 bits)
—
7
0
CCR3
Common Control Register 3
72h
—
6
0
—
5
0
—
4
0
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TDATFMT
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
TGPCKEN
2
0
RDATFMT
1
0
RGPCKEN
0
0