DS21458-W+ Maxim Integrated, DS21458-W+ Datasheet - Page 5

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DS21458-W+

Manufacturer Part Number
DS21458-W+
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS21458-W+

Product
Framer
Number Of Transceivers
4
Data Rate
64 Kbps
Supply Current (max)
328 mA
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
CSBGA
Minimum Operating Temperature
0 C
Operating Supply Voltage
3.3 V
Supply Voltage - Max
3.465 V
Supply Voltage - Min
3.135 V
Part # Aliases
90-21458+W00
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
24.6
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
27.1
27.2
27.3
27.4
28.1
29.1
29.2
35.1
35.2
35.3
35.4
35.5
36.1
36.2
38.1
38.2
38.3
38.4
24.5.1
24.5.2
25.2.1
25.2.2
25.2.3
25.3.1
25.3.2
25.3.3
25.3.4
28.1.1
LINE INTERFACE UNIT (LIU) ................................................................................................................... 158
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ..................................... 179
BERT FUNCTION ...................................................................................................................................... 186
PAYLOAD ERROR INSERTION FUNCTION ........................................................................................... 195
INTERLEAVED PCM BUS OPERATION .................................................................................................. 199
EXTENDED SYSTEM INFORMATION BUS (ESIB) ................................................................................. 202
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER .................................................................... 208
FRACTIONAL T1/E1 SUPPORT ............................................................................................................... 209
USER-PROGRAMMABLE OUTPUT PINS ............................................................................................... 210
TRANSMIT FLOW DIAGRAMS................................................................................................................. 211
JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT ............................................ 216
FUNCTIONAL TIMING DIAGRAMS.......................................................................................................... 228
OPERATING PARAMETERS.................................................................................................................... 251
AC TIMING PARAMETERS AND DIAGRAMS......................................................................................... 253
PACKAGE INFORMATION ....................................................................................................................... 269
D4/SLC-96 O
LIU O
LIU R
LIU T
MCLK P
J
CMI (C
LIU C
R
C
BERT R
BERT R
BERT B
BERT E
N
C
F
I
T
B
B
I
T1 M
E1 M
M
N
R
T
NSTRUCTION
DENTIFICATION
ITTER
RAME
EST
RANSMIT
OUNDARY
YPASS
ECOMMENDED
OMPONENT
UMBER OF
HANNEL
ONMULTIPLEXED
ECEIVE
ULTIPLEXED
ODE
ODE
RANSMITTER
R
ECEIVER
ONTROL
PERATION
Receive Section ............................................................................................................155
Transmit Section ...........................................................................................................157
Receive Level Indicator................................................................................................160
Receive G.703 Section 10 Synchronization Signal .................................................160
Monitor Mode.................................................................................................................160
Transmit Short-Circuit Detector/Limiter .....................................................................161
Transmit Open-Circuit Detector ..................................................................................161
Transmit BPV Error Insertion ......................................................................................162
Transmit G.703 Section 10 Synchronization Signal (E1 Mode).............................162
Number of Errors Left Register...................................................................................198
A
ODE
EGISTERS
I
NTERLEAVE
IT
RROR
R
EGISTER
EPETITIVE
RESCALER
TTENUATOR
S
........................................................................................................................ 228
........................................................................................................................ 238
I
EGISTER
AC C
C
NTERLEAVE
IDE
S
M
E
OUNTER
CAN
S
R
RROR
ARK
PERATION
B
................................................................................................................. 159
R
C
AC C
PECIFICATIONS
EGISTER
R
US
HARACTERISTICS
EGISTERS
C
.............................................................................................................. 159
OUNTER
............................................................................................................. 222
D
EGISTER
R
IRCUITS
B
........................................................................................................... 161
I
P
.......................................................................................................... 162
.......................................................................................................... 222
AC C
NVERSION
ESCRIPTION
EGISTER
US
R
M
HARACTERISTICS
ATTERN
....................................................................................................... 162
....................................................................................................... 193
EGISTERS
ODE
M
AC C
.................................................................................................. 157
.................................................................................................. 220
ODE
HARACTERISTICS
................................................................................................. 194
................................................................................................ 173
............................................................................................... 164
............................................................................................... 199
............................................................................................... 222
............................................................................................ 222
S
HARACTERISTICS
........................................................................................... 199
) O
.......................................................................................... 175
ET
........................................................................................ 187
....................................................................................... 197
PTION
..................................................................................... 192
..................................................................................... 265
............................................................................... 259
............................................................................ 163
........................................................................ 253
.................................................................. 256
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DS21455/DS21458 Quad T1/E1/J1 Transceivers

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