ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 81

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 40. Pin Descriptions (Continued)
TDI, TCK, TMS
RDY/BUSY/RCLK
HDC
LDC
INIT
CS0, CS1
RD/MPI_STRB
WR/MPI_RW
PPC_A[14:31]
MPI_BURST
MPI_BDIP
MPI_TSZ[0:1]
A[21:0]
MPI_ACK
Symbol
I/O
I/O After configuration, these pins are user-programmable I/O if boundary scan is not used.
I/O After configuration this pin is a user-programmable I/O pin.
I/O After configuration, this pin is a user-programmable I/O pin.
I/O After configuration, this pin is a user-programmable I/O pin.
I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is
I/O After configuration, if MPI is not used, these pins are user-programmable I/O pins.
I/O After configuration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.
O During configuration in asynchronous peripheral mode, RDY/RCLK indicates another byte can
O High During Configuration is output high until configuration is complete. It is used as a control
O Low During Configuration is output low until configuration is complete. It is used as a control out-
O During master parallel mode A[21:0] address the configuration EPROMs up to 4M bytes.
O In
I
I
I
I
I
I
I
I
If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If
boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is
complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during
configuration. Each pin has a pull-up enabled during configuration.
be written to the FPGA. If a read operation is done when the device is selected, the same sta-
tus is also available on D7 in asynchronous peripheral mode.
During the master parallel configuration mode, RCLK is a read output signal to an external
memory. This output is not normally used.
output, indicating that configuration is not complete.
put, indicating that configuration is not complete.
enabled, but an external pull-up resistor is recommended. As an active-low open-drain output,
INIT is held low during power stabilization and internal clearing of memory. As an active-low
input, INIT holds the FPGA in the wait-state before the start of configuration.
After configuration, this pin is a user-programmable I/O pin.
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor con-
figuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configura-
tion, a pull-up is enabled.
RD is used in the asynchronous peripheral configuration mode. A low on RD changes D[7:3]
into a status output. WR and RD should not be used simultaneously. If they are, the write strobe
overrides.
This pin is also used as the
ready, and a low indicates busy.
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the
FPGA.
In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write
transfer to the FPGA.
During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC bus
master utilizing the least-significant bits of the PowerPC 32-bit address.
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high
indicates that the current transfer is not a burst.
MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates that
the second beat in front of the current one is requested by the master. Negated before the burst
transfer ends to abort the burst data phase.
MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer
size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
returned data on a read cycle.
MPI
mode this is driven low indicating the MPI received the data on the write cycle or
MPI
81
data transfer strobe. As a status indication, a high indicates
ORCA ORT42G5 and ORT82G5 Data Sheet
Description
1
1
1
1
1
1
1
1
1