ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 27

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Multi-channel Alignment
The alignment FIFO allows the transfer of all data to the system clock. The Multi-Channel Alignment block
(Figure 6) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams.
This optional alignment ensures that matching SERDES streams will arrive at the FPGA end in perfect data syn-
chronization.
Each channel is provided with a 24 word x 36-bit FIFO. The FIFO can perform two tasks: (1) to change the clock
domain from receive clock to a clock from the FPGA side, and (2) to align the receive data over 2, 4, or 8 channels.
This FIFO allows a timing budget of ±230.4 ns that can be allocated to skew between the data lanes and for trans-
fer to the system clock. The input to the FIFO consists of 36 bits of demultiplexed data, RALIGN_xx[3:0],
RWD_xx[31:0], and RWBIT8_xx[3:0].
The four RALIGN_xx bits are control signals, and can be the alignment character detect signals indicating the pres-
ence of a comma character in Fibre Channel mode and the /A/ character in XAUI mode. The other 32 RWD_xx bits
are the 8-bit data bytes from the 8b/10b decoder. The alignment character, if present, is the MSB of the data. The
RWBIT8_xx indicates the presence of a Km.n control character in the receive data byte. Only RWBIT8_xx and
RWD_xx inputs are stored in the FIFO. During alignment process, RALIGN[3]_xx is used to synchronize multiple
channels.
If a channel is not in any alignment group, it will set the FIFO-write-address to the beginning of the FIFO, and will
set the FIFO-read-address to the middle of the FIFO, at the first assertion of RALIGN[3]_xx after reset or after the
resync command.
The RX_FIFO_MIN_xx register bits can be used to control the threshold for minimum unused buffer space in the
alignment FIFOs between read and write pointers before overflow (OVFL) status is flagged. The synchronization
algorithm consists of a down counter which starts to count down by 1 from its initial value of 18 (decimal) when an
alignment character from any channel within an alignment group has been received. Once all the alignment char-
acters within the alignment group have been received, the count is decremented by 2 until 0 is reached. Data is
then read from the FIFOs and output to the FPGA. This algorithm is not repeated after multi-channel alignment has
been achieved; resynchronization must be forced by toggling the appropriate FMPU_RESYNC bit.
ORT42G5 Multi-channel Alignment
The ORT42G5 has a total of four channels. The incoming data of these channels can be synchronized in two ways
or they can be independent of one other. Two channels, C and D, within either SERDES block can be aligned
together to form a pair, as shown in Figure 11. Alternately, all four channels can be aligned together to form a com-
munication channel with a bandwidth of 10 Gbps, as shown in Figure 12. Individual channels within an alignment
group can be disabled (i.e., powered down) without disrupting other channels.
Figure 11. Dual Channel Alignment
Channel BC
Channel AC
Channel BD
Channel AD
D
D
UAL ALIGNMENT OF CHANNELS AC AND AD
UAL
A
LIGNMENT OF CHANNELS BC AND BD
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ORCA ORT42G5 and ORT82G5 Data Sheet
Channel BC
Channel BD
Channel AD
Channel AC
t
1
t
0