ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 77

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
High Speed Data Receiver
Table 35 specifies receiver parameters measured on devices with worst case process parameters and over the full
range of operation conditions.
Table 35. External Data Input Specifications
Input Data Jitter Tolerance
A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-
dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler-
ance levels for different jitter types as they relate to specific protocols (e.g XAUI, FC, Infiniband etc.). Sinusoidal
jitter is considered to be a worst case jitter type. Table 36 shows receiver specifications with 10 MHz sinusoidal jit-
ter injection. XAUI specific jitter tolerance measurements were measured in a separate experiment detailed in tech-
nical note TN1032, SERDES Test Chip Jitter, and are not reflected in these results.
Table 36. Receiver Sinusoidal Jitter Tolerance Specifications
Input Data
Stream of Nontransitions
Sensitivity (differential), worst-case
Input Levels
Internal Buffer Resistance (Each input to VDDIB)
PLL Lock Time
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., T
2. Input level min + (input peak to peak swing)/2 ≤ common mode input voltage ≤ input level max - (input peak to peak swing)/2
3. The ORT42G5 and ORT82G5 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing first
ply.
bit, then byte (character), then channel (32-bit word), and finally optional multi-channel alignment as described in TN1025. The PLL Lock
Time is the time required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream. If the PLL is unable to
lock to the serial data stream, it instead locks to REFCLK to stabilize the voltage-controlled oscillator (VCO), and periodically switches back
to the serial data stream to again attempt synchronization.
Input Data
Jitter Tolerance @3.125Gbps, Typical
Jitter Tolerance @3.125Gbps, Worst case
Jitter Tolerance @2.5Gbps,Typical
Jitter Tolerance @2.5Gbps, Worst case
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., T
to 1.575V supply. Jitter measured with a Wavecrest SIA-3000.
2
3
Parameter
Parameter
1
8b/10b encode/decode off
Conditions
3.125 Gbps
77
—
—
—
ORCA ORT42G5 and ORT82G5 Data Sheet
600 mV diff eye
600 mV diff eye
600 mV diff eye
600 mV diff eye
Conditions
V
SS
Min.
1
1
1
1
80
40
—
—
- 0.3
A
Typ.
= 0
50
—
—
—
—
o
C to 85
A
Max.
0.75
0.65
0.79
0.67
= 0
V
DD_ANA
o
C to 85
o
C, 1.425V to 1.575V sup-
Note 2
Max.
72
60
—
o
+ 0.3
C, 1.425V
U
U
U
U
Unit
IP-P
IP-P
IP-P
IP-P
mVp-p
Units
Bits
—
V
Ω