ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 2

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table of Contents
Introduction .................................................................. 1
Table of Contents......................................................... 2
Embedded Function Features...................................... 4
Programmable Features .............................................. 5
Programmable Logic System Features........................ 6
Description ................................................................... 7
System-Level Features ................................................ 9
ORT42G5/ORT82G5 Overview ................................. 11
Backplane Transceiver Core Detailed Description .... 13
Multi-channel Alignment............................................. 27
Multi-channel Alignment Configuration ...................... 30
Reference Clocks and Internal Clock Distribution...... 37
What is an FPSC?........................................... 7
FPSC Overview............................................... 7
FPSC Gate Counting ...................................... 7
FPGA/Embedded Core Interface .................... 7
FPSC Design Kit ............................................. 7
FPGA Logic Overview..................................... 8
PLC Logic........................................................ 8
Programmable I/O........................................... 8
Routing............................................................ 9
Microprocessor Interface................................. 9
System Bus ................................................... 10
Phase-Locked Loops .................................... 10
Embedded Block RAM .................................. 10
Configuration................................................. 10
Additional Information ................................... 11
Embedded Core Overview ............................ 11
Serializer and Deserializer (SERDES) .......... 11
MUX/DEMUX Block ...................................... 12
Multi-channel Alignment FIFOs..................... 12
XAUI and Fibre Channel Link State
Machines....................................................... 12
FPGA/Embedded Core Interface .................. 12
Dual Port RAMs ............................................ 13
FPSC Configuration ...................................... 13
8b/10b Encoding and Decoding .................... 14
Transmit Path (FPGA to Backplane) Logic ... 16
8b/10b Encoder and 1:10 Multiplexer ........... 18
CML Output Buffer ........................................ 18
Receive Path (Backplane to FPGA) Logic .... 19
Link State Machines...................................... 24
XAUI Link Synchronization Function............. 25
ORT42G5 Multi-channel Alignment .............. 27
ORT82G5 Multi-channel Alignment .............. 28
XAUI Lane Alignment Function
Mixing Half-rate, Full-rate Modes .................. 30
ORT42G5 Configuration ............................... 30
ORT82G5 Configuration ............................... 31
ORT42G5 Alignment Sequence.................... 32
ORT82G5 Alignment Sequence.................... 33
(Lane Deskew) ....................................... 29
2
Internal Clock Signals at the FPGA/Core Interface
Internal Clock Signals at the FPGA/Core Interface
Reset Operation ......................................................... 49
Test Modes ................................................................ 52
Embedded Core Block RAM ...................................... 56
Memory Maps ............................................................ 59
Absolute Maximum Ratings ....................................... 75
Recommended Operating Conditions ........................ 75
SERDES Electrical and Timing Characteristics ......... 75
Pin Descriptions ......................................................... 80
Power Supplies for ORT42G5 AND ORT82G5.......... 85
Package Information .................................................. 87
ORCA ORT42G5 and ORT82G5 Data Sheet
for the ORT42G5 ................................................. 38
for the ORT82G5 ................................................. 43
Reference Clock Requirements .................... 37
Synthesized and Recovered Clocks ............. 37
Transmit and Receive Clock Rates............... 39
Transmit Clock Source Selection .................. 39
Recommended Transmit Clock Distribution
Multi-Channel Alignment Clocking
Transmit and Receive Clock Rates............... 44
Transmit Clock Source Selection .................. 44
Recommended Transmit Clock Distribution
Multi-Channel Alignment Clocking
Start Up Sequence for the ORT42G5 ........... 50
Start Up Sequence for the ORT82G5 ........... 51
Loopback Testing.......................................... 52
High-Speed Serial Loopback at the CML
Parallel Loopback at the SERDES
Parallel Loopback at MUX/DEMUX
SERDES Characterization Test Mode
Definition of Register Types .......................... 59
ORT42G5 Memory Map................................ 59
ORT82G5 Memory Map................................ 67
Recommended Board-level Clocking for
High Speed Data Transmitter........................ 76
High Speed Data Receiver............................ 77
External Reference Clock ............................. 79
Embedded Core Timing Characteristics ....... 79
Power Supply Descriptions ........................... 85
Recommended Power Supply
Recommended Power Supply Filtering
Package Pinouts ........................................... 87
for the ORT42G5 .................................... 39
Strategies for the ORT42G5 ................... 41
for the ORT82G5 .................................... 45
Strategies for the ORT82G5 ................... 47
Buffer Interface ....................................... 53
Boundary ................................................ 54
Boundary, Excluding SERDES ............... 55
(ORT82G5 Only)..................................... 55
the ORT42G5 and ORT82G5 ................. 73
Connections............................................ 85
Scheme................................................... 85