ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 30

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 16. Deskew Lanes by Aligning /A/ Columns
Mixing Half-rate, Full-rate Modes
When channel alignment is enabled, all receive channels within an alignment group should be configured at the
same rate. For example, in the ORT82G5 channels AA, AB, can be configured for twin alignment and full-rate
mode, while channels AC, AD that form an alignment group can be configured for half-rate mode. In block align-
ment mode, each receive block can be configured in either half or full-rate mode.
When channel alignment is disabled within a block, any receive channel within the block can be used in half-rate or
full-rate mode. The clocking strategy for half-rate mode in both scenarios (channel alignment enabled or disabled)
is described in the Reference Clocks and Internal Clock Distribution sections later in this data sheet.
Multi-channel Alignment Configuration
ORT42G5 Configuration
At startup, the legacy SERDES channel logic must be powered down and removed from any multi-channel align-
ment groups:
• Setting bit 1 to one in registers at locations 30002, 30012, 30102, 30112, 30003, 30013, 30103 and 30113 pow-
• Setting bits 4 and 5 to zero (reset condition) in the register at locations 30810 and 30910 removes the legacy
Register settings for multi-channel alignment are shown in Table 6.
Table 6. Multichannel Alignment Modes
To align two channels in SERDES A:
• FMPU_SYNMODE_A = 00001010 (Register Location 30811)
To align two channels in SERDES B:
• FMPU_SYNMODE_B = 00001010 (Register Location 30911)
To align all four channels:
• FMPU_SYNMODE_A = 00001111 (Register Location 30811)
ers down the legacy logic. (Note that the reset value for these bits is 0.)
logic from any alignment group.
LANE 0
LANE 2
LANE 0
LANE 1
LANE 2
LANE 3
K
FMPU_SYNMODE_[A:B][0:7]
LANE 1
R
K
K
K
K
K
R
LANE 3
R
R
R
R
R
Register Bits
K
00000000
00001010
00001111
K
R
R
R
R
R
R
R
K
K
K
K
K
K
K
R
R
R
R
R
R
A
R
K
K
K
K
K
K
R
R
R
A
A
A
A
A
K
K
K
R
R
R
R
R
K
30
R
A
No multichannel alignment.
Twin channel alignment.
Four channel alignment.
K
K
K
K
K
R
K
ORCA ORT42G5 and ORT82G5 Data Sheet
R
K
K
K
K
K
K
A
K
R
R
R
R
R
R
R
K
K
K
K
K
K
R
K
Mode
R
R
R
R
R
R
K
K
K
R
R
R
R
R
R
R
K
K
K
K
K
K
R
R
K
R
K