ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 67

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ORT82G5 Memory Map
Each ORT82G5 SERDES block has eight independent channels. Each channel is identified by both a quad identi-
fier, A or B, and a channel identifier, A, B, C or D. The registers in ORT82G5 are 8-bit memory locations, which can
be classified into Status Register and Control Register.
Status Register
Read-only register to convey the status information of various operations within the FPSC core. An example is the
state of the XAUI link-state-machine.
Control Register
Read-write register to set up the control inputs that define the operation of the FPSC core.
Reserved addresses for the FPSC register blocks are shown in Table 29.
Table 29. Structural Register Elements
Table 30 details the memory map for the FPSC portion of the ORT82G5 device. In both Table 29 and Table 30, the
addresses are given as 18-bit hexadecimal (18’h) values. The address may be sourced either through the Micro-
processor interface or a User Master Interface. The MicroProcessor Interface (MPI) address bus is a 32-bit bus
which follows the Power PC convention where address bit 0 is the MSb and address bit 31 is the LSb. The MPI
maps bits MPI_ADDR[14:31] to bits [17:0] of the system address bus. The User Master Interface (UMI) has an 18-
bit address bus and uses the opposite notation, where address line 17 is the MSb and address line 0 is the LSb.
The UMI maps bits um_addr[17:0] to bits [17:0] of the system address bus. Because of the address mapping done
by the MPI and UMI, the same hexadecimal address value is valid for both interfaces.
The UMI, internal and microprocessor interface data buses have both 32-bit data and 4-bit parity fields and the
data fields are mapped 1:1 to each other, i.e., bit 0 is bit 0 for all three buses. The bit ordering is specific to the tar-
geted functional block. In the memory map, only bits [0:7] are specified and the convention followed for sub-field
descriptions is to map the bits in the description directly to the bit order given in the bit column. For example, to
select channel C as the source for the transmit and receive clocks, the register at location 30A00 should have bits
0, 2, 4 and 6 set to zero and bits 1, 3, 5 and 7 set to one.
In the example in the previous paragraph, the bits being set are control bits and are independent of the MSb/LSb
convention used. The resulting bit pattern 01010101 maps to the hexadecimal value AA if the left-most bit is con-
sidered the LSb and to 55 if the right-most bit is considered the LSb. In some cases, however, the data represents
the value of a specific parameter, such as a size or threshold level, and the value may be stored at more than one
address location, since each location can hold only 8 bits of data. For a given register, either the MSb or the LSb bit
position is specified explicitly in the memory map. If the parameter value extends over multiple register locations,
the relative bit or byte ordering is also specified. For additional information on the MPI and the system bus, see
Technical Note TN1017, ORCA Series 4 MPI/System Bus.
Address (0x)
30A0x
300xx
301xx
308xx
309xx
SERDES A, internal registers.
SERDES B, internal registers.
Channel A [A:D] registers (external to SERDES blocks).
Channel B [A:D] registers (external to SERDES blocks).
Global registers (external to SERDES blocks).
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ORCA ORT42G5 and ORT82G5 Data Sheet
Description