ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 71

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Table 30. ORT82G5 Memory Map (Continued)
Lattice Semiconductor
30810 - Ax
30910 - Bx
30811 - Ax
30911 - Bx
30820 - Ax
30920 - Bx
30821 - A
30921 - B
30933
Status Registers (Read Only), xx=[AA,...,BD]
30804 - Ax
30904 - Bx
Absolute
Address
(0x)
[5] xC & xD
xA & xB
[0]xA
[1]xB
[2]xC
[3]xD
[4]xA
[5]xB
[6]xC
[7]xD
[0]xA
[1]xB
[2]xC
[3]xD
[0:1]
[2:3]
[4:5]
[6:7]
[1:7]
[0:3]
[4:5]
[0:1]
[2:3]
[4:5]
[6:7]
Bit
xA
xB
xC
xD
xA
xB
xC
xD
[4]
[6]
[7]
[0]
[6]
[7]
DOWDALIGN_xx
FMPU_STR_EN
_xx
FMPU_SYNMOD
E_xx[0:1]
FMPU_RESYNC1
_xx
FMPU_RESYNC2
_x[1:2]
FMPU_RESYNC4
[A:B]
XAUI_MODE[A:B]
NOCHALGN [A:B]
Reserved for future use.
Reserved for future use.
SCHAR_CHAN[0:
1]
SCHAR_TXSEL
SCHAR_ENA
XAUISTAT_xx[0:1]
Name
Reset
Value
(0x)
00
00
00
00
00
00
Word Realign Bit. When DOWDALIGN_xx transitions from 0 to 1, the
receiver realigns on the next comma character for Channel xx.
NOWDALIGN_xx=0 on device reset.
Enable multi-channel alignment for Channel xx. When
FMPU_STR_EN_xx=1, the corresponding channel participates in multi-
channel alignment. FMPU_STR_EN_xx=0 on device reset.
Sync mode for xx
00 = No channel alignment
10 = Twin channel alignment
01 = Quad channel alignment
11 = Eight channel alignment
Resync a Single Channel. When FMPU_RESYNC1_xx transitions from
0 to 1, the corresponding channel is resynchronized (the write and read
pointers are reset). FMPU_STR_EN_xx=0 on device reset.
Resync a Pair of Channels. When FMPU_RESYNC2_[A:B][1:2] transi-
tions from a 0 to a 1, the corresponding channel pair is resynchronized.
FFMPU_RESYNC2_[A:B][1:2]=0 on device reset.
Resync a Four-Channel Group. When FMPU_RESYNC4[A:B] transitions
from a 0 to a 1, the corresponding four-channel group is resynchronized.
FMPU_RESYNC4[A:B]=0 on device reset.
Controls use of XAUI link state machine in place of Fibre-Channel state
machine. When XAUI_MODE[A:B]=1, all four channels in the SERDES
quad enable their XAUI link state machines. (LINKSM_xx bits are
ignored). XAUI_MODE[A:B]=0 on device reset.
Bypass channel alignment. NOCHALGN [A:B] =1 causes bypassing of
multi-channel alignment FIFOs for the corresponding SERDES quad.
Select channel to test
00 = Channel BA
10 = Channel BB
01 =Channel BC
11 = Channel BD
1=Select TX option
0=Select RX option
1=Enable Characterization of SERDES B
XAUI Status Register. Status of XAUI link state machine for Channel xx
00 – No synchronization.
10 – Synchronization done.
11 – Not used.
01 – no_comma (see XAUI state machine) and at least one CV detected
XAUISTAT_xx[0:1] = 00 on device reset.
NOCHALGN [A:B] =0 on device reset.
71
ORCA ORT42G5 and ORT82G5 Data Sheet
Description