ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 47

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
The receive channel alignment bypass mode allows mixing of half and full line rates among the channels, as shown
in Figure 28. The figure shows channel pair AA and AB configured in full rate mode at 2.0 Gbps. Channel pair AC
and AD are configured in half-rate mode at 1.0 Gbps.
Figure 28. Receive Clocking for Mixed Line Rates
As noted in the caption of Figure 28, each quad can be configured in any line rate (0.6 to 3.7 Gbps), since each
quad has its own reference clock input pins. The receive alignment FIFO per channel cannot be used in this mode.
Multi-Channel Alignment Clocking Strategies for the ORT82G5
The data on the eight channels (four per SERDES quad) in the ORT82G5 can be independent of each other or can
be synchronized in several ways. For example, two channels within a SERDES can be aligned together; channel A
and B and/or channel C and D. Alternatively, all four channels in a SERDES quad can be aligned together to form a
communication channel with a bandwidth of 10 Gbps. Finally, the alignment can be extended across both SERDES
quads to align all eight channels. Individual channels within an alignment group can be disabled (i.e., powered
down) without disrupting other channels. Clocking strategies for these various modes are described in the following
paragraphs.
For dual alignment both twins within a quad can be sourced by clocks that are different from the other channels,
however each pair of SERDES must have the same clock. The channel pair AA and AB is driven on the low speed
side by RSYS_CLK_A1 and the channel pair AC and AD are driven on the low speed side by RSYS_CLK_A2.
Either RWCKAA or RWCKAB can be connected to RSYS_CLK_A1 and either RWCKAC or RWCKAD can be con-
nected to RSYS_CLK_A2. A clocking example for dual alignment is shown in Figure 29.
Recovered
Recovered
Clocks at
Clocks at
50 MHZ
FPGA
Logic
25 MHZ
or 50 MHz
25 MHz
{
{
RSYS_CLK_A1
RSYS_CLK_A2
RWCKAA
RWCKAB
RWCKAC
RWCKAD
RCK78A
Common Logic, Quad A
Channel AD
Channel AA
Channel AB
Channel AC
47
ORCA ORT42G5 and ORT82G5 Data Sheet
2
REFCLK[P:N]_A
100 MHz
Incoming Serial Data
Incoming Serial Data
1.0 Gbps (Half-Rate)
2.0 Gbps (Full-Rate)
Two Channels of
Two Channels of