ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet
ORT82G5-1BM680C
Related parts for ORT82G5-1BM680C
ORT82G5-1BM680C Summary of contents
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... For example, designers can build a bridge for 10 G Ethernet: the high-speed SERDES interfaces can implement a XAUI interface with a configurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and protection links between a line card and switch fabric. ...
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... Recommended Transmit Clock Distribution for the ORT82G5 .................................... 45 Multi-Channel Alignment Clocking Strategies for the ORT82G5 ................... 47 Reset Operation ......................................................... 49 Start Up Sequence for the ORT42G5 ........... 50 Start Up Sequence for the ORT82G5 ........... 51 Test Modes ................................................................ 52 Loopback Testing.......................................... 52 High-Speed Serial Loopback at the CML Buffer Interface ....................................... 53 Parallel Loopback at the SERDES Boundary ...
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... Summary .............................................. 114 Θ .............................................................. 114 JA .............................................................. 114 ψ JC ψ .............................................................. 115 JC ψ .............................................................. 115 JB FPSC Maximum Junction Temperature ...... 115 Package Thermal Characteristics ............... 115 Heat Sink Vendors for BGA Packages........ 115 Package Parasitics...................................... 116 Package Outline Drawings.......................... 116 Ordering Information ................................................ 117 ORCA ORT42G5 and ORT82G5 Data Sheet 3 ...
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... Built-in boundary scan (IEEE interface. • FIFOs can align incoming data either across all eight channels (ORT82G5 only), across one or two groups of four channels, or across two or four groups of two channels. Alignment is done either using comma characters or by using the /A/ character in XAUI mode. Optionally, the alignment FIFOs can be bypassed for asynchronous operation between channels. (Each channel includes its own clock and frame pulse or comma detect.) • ...
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... New 200 MHz embedded block-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as: ORCA ORT42G5 and ORT82G5 Data Sheet ® -like AND-OR-Invert (AOI) in each pro- ...
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... New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high- speed memory interfaces. • New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal logic. ORCA ORT42G5 and ORT82G5 Data Sheet 6 ...
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... HSPICE and/or IBIS models for I/O buffers, and complete online documentation. The kit's software coupled with the design environment, provides a seamless FPSC design environment. More information can be obtained by vis- iting the Lattice web site at www.latticesemi.com or contacting a local sales office. ORCA ORT42G5 and ORT82G5 Data Sheet 7 ...
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... The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset, and global set/reset. On the input side, each PIO contains a programmable latch/Flip-Flop which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for ORCA ORT42G5 and ORT82G5 Data Sheet 8 ...
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... FIFOs. Transfer accesses can be single beat ( bytes or less), 4-beat ( bytes), 8-beat ( bytes), or 16-beat ( bytes). ORCA ORT42G5 and ORT82G5 Data Sheet ® PowerPC 860 bus, it can be used for configuration and ...
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... Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE 1149.2) port is also available meeting In-System Programming (ISP™) standards (IEEE 1532 Draft). ORCA ORT42G5 and ORT82G5 Data Sheet 10 ...
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... FPGA array. A top level diagram of the basic chip configuration is shown in Figure 1. Embedded Core Overview The embedded core portions of the ORT42G5 and ORT82G5 contain respectively four or eight Clock and Data Recovery (CDR) macrocells and Serialize/Deserialize (SERDES) blocks and support 8b/10b ( IEEE 802.3.2002) encoded serial links intended for high-speed serial backplane data transmission. Figure 1 shows the ORT42G5 and ORT82G5 top level block diagram and the basic data fl ...
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... FPGA logic. Multi-channel Alignment FIFOs In the ORT82G5, the eight incoming data channels (four per SERDES block) can be independent of each other or can be synchronized in several ways. Two channels within a SERDES block can be aligned together; channels A and B and/or channels C and D. Alternatively, four channels in a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbps ...
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... FPGA logic. A simple IP block that drives the system by using the user register interface and very little FPGA logic is available in the MPI/System Bus Technical Note. This IP block sets up the embedded core via a state machine and allows the ORT42G5 and ORT82G5 to work in an independent system without an external microprocessor interface. ...
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... FC-PH ANSI X3.230:1994 standard (which is also the encoding used by the IEEE 802.3ae Ethernet standard). This encoding/decoding scheme also allows for the transmission of special characters and supports error detection. ORCA ORT42G5 and ORT82G5 Data Sheet Common Logic, Block A Receive Channel AC ...
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... K28.6 110 11100 K28.7 /comma/ 111 11100 K23.7 111 10111 K27.7 111 11011 K29.7 111 11101 K30.7 111 11110 ORCA ORT42G5 and ORT82G5 Data Sheet Encoded Word (–) K Control abcdei fghj 1 001111 0100 1 001111 1001 1 001111 0101 1 001111 0011 1 ...
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... TWDxx[31:0] 32 TCOMMAxx[3:0] 4 TBIT9xx[3:0] 4 FIFO TSYS_CLK_xx ÷ TCK78[A:B] { MUX 78.125 MHz TCKSEL[0:1][A:B] ORCA ORT42G5 and ORT82G5 Data Sheet For ORT42G5 [AC, AD BD] For ORT82G5 [AA, AB, ... BD] STBD_xx[7:0] 8 8-bit data 8B/10B STBD_xx[8] Encoder K-control 4:1 MUX (with (x9) bypass) STBD_xx[9] Force-ve disparity PLL STBC311_xx 4 312 ...
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... A falling edge on the STBC311xx clock port will cause a new data charac- ter to be transferred into the SERDES block. The latency from the SERDES block input to the high-speed serial output is 5 STBC311xx clock cycles, as shown in Figure 5. ORCA ORT42G5 and ORT82G5 Data Sheet p t ...
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... FR4 material at 2.5 GHz, the attenuation compared to the 1.0 GHz value is about 3 dB. The attenuation is a result of skin effect loss of the PCB conductor and the dielectric loss of the PCB substrate. This attenuation causes inter- symbol interface which results in the closing of the data eye opening at the receiver. ORCA ORT42G5 and ORT82G5 Data Sheet p q ...
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... Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also degrade the data eye opening at the receiver. In the ORT42G5 and ORT82G5 the degree of transmit preemphasis can be programmed with a two-bit control from the microprocessor interface as shown in Table 3. The high-pass transfer function of the preemphasis circuit is given by the following equation, where the value shown in Table 3 ...
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... The CDR can maintain lock on data as long as the input data stream contains an adequate data “eye” (i.e., jitter is within specification) and the maxi- mum data stream run length is not exceeded. ORCA ORT42G5 and ORT82G5 Data Sheet SBYTSYNC_xx Fibre Channel State ...
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... In XAUI mode, as the state diagram later in this data sheet indicates, three error-free code-groups containing com- mas must be detected before synchronization is declared. Multi (ORT82G5 only) channel alignment (Lane alignment in XAUI mode) can be performed after 32- bit word alignment is complete. Multi-channel alignment is described in later sections of this data sheet. ...
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... Another task of the 1:4 DEMUX is to recognize the synchronizing event and adjust the 4-byte boundary so that the synchronizing character leads off a new 4-byte word. In Fibre Channel mode, this synchronizing character is a comma. This feature will be referred to as DEMUX word alignment in other areas of this document. DEMUX word ORCA ORT42G5 and ORT82G5 Data Sheet EMBEDDED CORE ..... ...
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... The relationship between a time sequence of values input at SRBDxx[7:0] to the values output at RWD_xx[39:0] is shown in Figure 8. A parallel relationship exists between SRBDx[8] and RWBIT8_xx[3:0] as well as between SRBD_xx[9] and RWBIT9_xx[3:0]. ORCA ORT42G5 and ORT82G5 Data Sheet 23 ...
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... WDSYNC_xx output which now transitions from this point the machine attempts to establish the link yet again. Figure 9 shows the state diagram for the Fibre Channel link state machine. LOS is also indicated by DEMUXWAS_xx status register bit. This bit is set to 0 during loss of synchronization. ORCA ORT42G5 and ORT82G5 Data Sheet q r ...
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... Indication that a valid code-group with the correct running disparity has been received. cg_bad Indication that an invalid code-group has been received. no_comma Indication that comma timer has expired. The timer is initialized upon receipt of a comma. ORCA ORT42G5 and ORT82G5 Data Sheet LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1) 1VW CV CV ...
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... OK cg_bad Sync_ Acq’d_2 gd_cg <= 0 cg_bad Sync_ Acq’d_3 gd_cg <= 0 cg_bad Sync_ Acq’d_4 gd_cg <= 0 cg_bad ORCA ORT42G5 and ORT82G5 Data Sheet Description reset Loss_of_Sync sync_status <= FAIL enable_CDET <= TRUE sync_complete Comma_Detect_1 enable_CDET <= FALSE cg_bad cg_comma Comma_Detect_2 ...
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... Gbps, as shown in Figure 12. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. Figure 11. Dual Channel Alignment Channel AC Channel AD Channel BC Channel ORCA ORT42G5 and ORT82G5 Data Sheet Channel AC Channel AD Channel BC Channel BD UAL ALIGNMENT OF CHANNELS AC AND AD A UAL LIGNMENT OF CHANNELS BC AND BD ...
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... QUAD ALIGNMENT OF CHANNELS AC ORT82G5 Multi-channel Alignment The ORT82G5 has a total of eight channels (four per SERDES block). The incoming data of these channels can be synchronized in several ways or they can be independent of one other. Two channels within a SERDES block can be aligned together. Channel A and B and/or channel C and D can form a pair as shown in Figure 13. Alternately, all four channels of a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbps as shown in Figure 14 ...
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... FIFO until all channels requesting alignment on the current device and all channels requesting alignment on the other device are aligned (as indicated on the K_CTRL character). These second alignment FIFOs will be implemented in FPGA logic on the ORT82G5. This scheme also requires that the reference clock for both devices be driven by the same signal. ...
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... When channel alignment is enabled, all receive channels within an alignment group should be configured at the same rate. For example, in the ORT82G5 channels AA, AB, can be configured for twin alignment and full-rate mode, while channels AC, AD that form an alignment group can be configured for half-rate mode. In block align- ment mode, each receive block can be confi ...
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... To resynchronize a multi-channel alignment group set the following bit to zero, and then set it to one: • FMPU_RESYNC8 for eight channel A[A:D] and B[A:D] • FMPU_RESYNC4A for quad channel A[A:D] • FMPU_RESYNC2A1 for twin channel A[A:B] ORCA ORT42G5 and ORT82G5 Data Sheet Register Bits 00 No multi-channel alignment. ...
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... If out-of-sync bit is 1, then rewrite the appropriate resync registers and monitor the OOS bit again. • If Out of Synchronization (OOS) bit is 0 but OVFL bit is 1, then check if the RX_FIFO_MIN value has been pro- ORCA ORT42G5 and ORT82G5 Data Sheet 32 ...
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... Change the value to 0 and check the OVFL bit again. If OOS and OVFL are 1, then rewrite the appropriate resync registers. The resync operation requires a rising edge. Two writes are required to the resync bits: write a 0 and then write a 1. ORCA ORT42G5 and ORT82G5 Data Sheet 33 ...
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... ORCA ORT42G5 and ORT82G5 Data Sheet 8b10bR=1 NOCHALGN[A:B]=1 CV_SELxx=1 CV_xx3, code violation, byte 3 K_CTRL for byte 3 bit 7 of byte3 bit 6 of byte 3 ...
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... OOS signal remaining low, the data being transferred across the core/FPGA interface is correctly aligned between channels. Note that only the signals corresponding to the selected alignment mode will be meaningful. Table 10. Definition of Status Bits of MRWDxx that Vary for Different Channels for the ORT82G5 Channel ...
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... Lattice Semiconductor Table 10. Definition of Status Bits of MRWDxx that Vary for Different Channels for the ORT82G5 (Continued) Channel Index Bit Index Name BA 29 CV_BA_OR BA 19 SYNC2_B1_OOS BB 29 CV_BB_OR BB 19 SYNC4_B_OOS BC 29 CV_BC_OR BC 19 SYNC2_B2_OOS BD 29 CV_BD_OR BD 19 SYNC8_OOS For the ORT82G5, the SYNC2_[A1,A2,B1,B2]_OOS, SYNC4_[A:B]_OOS,and SYNC8_OOS signals can be used with CH248_SYNC_xx to determine if the desired multi-channel alignment was successful ...
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... Reference Clocks and Internal Clock Distribution Reference Clock Requirements There are two pairs of reference clock inputs on the ORT42G5 and ORT82G5. The differential reference clock is distributed to all channels in a block. Each channel has a differential buffer to isolate the clock from the other chan- nels. The input clock is preferably a differential signal ...
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... B. To guarantee that there is no overflow in the alignment FIFO absolute requirement that the write and read clocks be frequency locked within 0 ppm. Examples of how to achieve this are shown in the later section on recommended board-level clocking. ORCA ORT42G5 and ORT82G5 Data Sheet 2 REFCLK[P:N]_A ...
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... As an example of the recommended clock distribution approach, TSYS_CLK_A can be sourced by TCK78A as shown in Figure 18 if the transmit line rate are common for both channels in a block. Similar clocking would be used for Block B. ORCA ORT42G5 and ORT82G5 Data Sheet TCK78[A: B] and RCK78[A:B] Clocks ...
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... In the receive channel alignment bypass mode the data and recovered clocks for the four channels are indepen- dent. The data for each channel are synchronized to the recovered clock from that channel. Figure 21 shows the recommended receive clocking for a single block. ORCA ORT42G5 and ORT82G5 Data Sheet 2 Common Logic, Block A ...
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... Clocking strategies for these various modes are described in the following para- graphs. For dual alignment both channels must be sourced by the same clock. Either RWCKAC or RWCKAD can be con- nected to RSYS_CLK_A2. A clocking example for dual alignment is shown in Figure 22. ORCA ORT42G5 and ORT82G5 Data Sheet RCK78A Common Logic, Block A RWCKAC ...
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... For quad alignment, either RCK78A or RCK78B can be used to source RSYS_CLK_[A:B]2 as shown in Figure 23. Figure 23. Clocking for Quad Alignment RSYS_CLK_A2 TSYS_CLK_AC TSYS_CLK_AD FPGA Logic RSYS_CLK_B2 TSYS_CLK_BC TSYS_CLK_BD All Clocks at 78.125 MHz ORCA ORT42G5 and ORT82G5 Data Sheet RCK78A TCK78A Common Logic, Block A Channel AC RWCKAD Channel AD RCK78A TCK78A Common Logic, Block A RWCKAC Channel AC ...
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... Internal Clock Signals at the FPGA/Core Interface for the ORT82G5 There are several clock signals defined at the FPGA/Embedded Core interface in addition to the external reference clock for each SERDES quad. All of the ORT82G5 clock signals are shown in Figure 24 and are described follow- ing the figure. ...
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... Thus, the recovered receive clocks are asynchronous between channels. Transmit Clock Source Selection The TCKSEL[0:1][A:B] bits select the source channel of TCK78[A:B]. The selection of the source for TCK78[A:B] is controlled by these bits as shown in Table 17. ORCA ORT42G5 and ORT82G5 Data Sheet TCK78[A: B] and RCK78[A:B] Clocks 60 MHz ...
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... Table 17. TCK78[A:B] Source Selection TCKSEL0 Recommended Transmit Clock Distribution for the ORT82G5 As an example of the recommended clock distribution approach, TSYS_CLK_A[A:D] can be sourced by TCK78A as shown in Figure 25 if the transmit line rate are common for all four channels in a quad. Similar clocking would be used for Quad B ...
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... DES quad) are independent. The data for each channel are synchronized to the recovered clock from that channel. Figure 27. - Receive Clocking for a Single Quad (Similar Connections Would Be Used for Quad B) 78.125 MHz FPGA RSYS_CLK_A1 Logic All Recovered Clocks at 78.125 MHZ RSYS_CLK_A2 ORCA ORT42G5 and ORT82G5 Data Sheet TCK78A Common Logic, Quad A Channel AA Channel AB Channel AC Channel AD RCKSEL1 0 0 ...
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... The receive alignment FIFO per channel cannot be used in this mode. Multi-Channel Alignment Clocking Strategies for the ORT82G5 The data on the eight channels (four per SERDES quad) in the ORT82G5 can be independent of each other or can be synchronized in several ways. For example, two channels within a SERDES can be aligned together; channel A and B and/or channel C and D ...
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... RSYS_CLK_A1 FPGA TSYS_CLK_AA Logic RWCKAB TSYS_CLK_AB RWCKAC TSYS_CLK_AC RWCKAD RSYS_CLK_A2 TSYS_CLK_AD All Clocks at 78.125 MHZ ORCA ORT42G5 and ORT82G5 Data Sheet 2 Common Logic, Quad A REFCLK[P:N]_A 156.25 MHz Channel AA Two Bidirectional Channels Channel AB Channel AC Two Bidirectional Channels Channel AD 2 Common Logic, Quad A REFCLK[P:N]_A 156 ...
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... GSWRST bit is deasserted. Note that the software reset option resets only SERDES internal registers and counters. The microprocessor registers are not affected. It should also be noted that the embedded block cannot be accessed until after FPGA configuration is complete. ORCA ORT42G5 and ORT82G5 Data Sheet 2 Common Logic, Quad A ...
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... If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three times: – K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma mode. – /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI mode. ORCA ORT42G5 and ORT82G5 Data Sheet 50 ...
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... Lattice Semiconductor Start Up Sequence for the ORT82G5 The following sequence is required by the ORT82G5 device. For information required for simulation that may be dif- ferent than this sequence, see the ORT82G5 Design Kit. 1. Initiate a hardware reset by making PASB_RESETN low. Keep this low during FPGA configuration of the device. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN. 2. Confi ...
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... The loopback mode can also be characterized by the physical location of the loopback connection. There are three possible loopback modes supported by the Embedded Core logic: • High-speed serial loopback at the CML buffer interface (near end) • Parallel loopback at the SERDES boundary (far end) ORCA ORT42G5 and ORT82G5 Data Sheet Device Under Test (DUT) FPGA Logic m ...
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... Bit (Channel C) Bit (Channel D) *This test mode can also be set using TESTEN_xx in place of LOOPENB_xx. In that case, Test Mode must be set to 00000. Table 20. High-Speed Serial Loopback Configuration Bit Definitions for the ORT82G5 Register Address Bit Value 30002, 30012, 30022, ...
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... Bit 30123, 30133 Bit 30005, 30105 Bit 30026, 30036, Bits[4:0] 30126, 30136 Table 22. Parallel Loopback at the SERDES Boundary Configuration Bit Definitions for the ORT82G5 Register Address (Hex) Bit Value 30002, 30012, Bit 30022, 30032, Bit ...
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... This test mode is enabled by setting the pin PLOOP_TEST_ENN to 0. PASB_TESTCLK must be running in this mode at 4x frequency of RSYS_CLK[A2, B2] or TSYS_CLK_[AC, AD, BC, BD] for the ORT42G5 and RSYS_CLK[A1,A2,B1,B2] or TSYS_CLK_[AA, AB... BD] for the ORT82G5. SERDES Characterization Test Mode (ORT82G5 Only) The SERDES characterization mode is a test mode that allows for direct control and observation of the transmit and receive SERDES interfaces at chip ports ...
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... Although the memory blocks/slices are in the EAC part of the chip, they do not interact with the rest of the EAC cir- cuits, but are standalone memories designed specifically to increase RAM capacity in the ORT82G5 chip. They can be used by logic implemented in the FPGA portion of the FPSC. Figure 34 represents one of the two available memory slices built into the EAC. The index “ ...
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... These SDRAMS should not be confused with the FPGA SDRAMS, which are generated through Module Generator in ispLEVER. The EAC SDRAMs are always built-in to the embedded core section of the ORT82G5/42G5 and their pins are accessed through the EAC interface. In order for these pins to be available at the interface in the gener- ated HDL models from ispLEVER, the “ ...
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... Figure 36. Minimum Timing Specs for Memory Blocks-Read Cycle (-1 Speed Grade) CKR AR[10:0], CSR Q[35:0] In Table 26, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core. ORCA ORT42G5 and ORT82G5 Data Sheet 2.0 ns 1.5 ns 0.5 ns 0.3 ns 0.5 ns 0.3 ns ...
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... Each ORT42G5 SERDES block has two independent channels. Each channel is identified by both a quad identi- fier and a channel identifier (This naming convention follows that of the ORT82G5.) The registers in ORT42G5 are 8-bit memory locations, which can be classified into Status Register and Control Register. ...
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... BC 30131 - BD [3] Reserved [4] Reserved [5] Reserved [6] Reserved [7] Reserved ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Reserved Receive PLL Lock Indication, Channel xx. LKI_xx = 1 indicates the receive PLL is locked. Reserved Reserved Not used FF Reserved, must be set to 1. Set device reset. ...
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... PWRDNR_xx [2] Reserved [3] 8b10bR_xx [4] LINKSM_xx [5:7] Not used ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Transmit Half Rate Selection Bit, Channel xx. When TXHR_xx = 1, HDOUT_xx's baud rate = (REFCLK[A:B]*10) and TCK78[A:B] =(REF- CLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's baud rate = (REF- CLK[A:B]*20) and TCK78[A:B]=(REFCLK[A:B]/2). TXHR_xx = 0 on device reset ...
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... Not used [7] GTESTEN_[A:B] 30006 - A [0:4] TestMode[A:B] 30106 - B [5] Not used [6:7] Reserved ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) See Reserved, must be 0. Set device reset. Bit Transmit and Receive Alarm Mask Bit, Channel xx. When MASK_xx = 1, Desc. the transmit and receive alarms of a channel are prevented from gener- ating an interrupt (i ...
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... LOOPENB_xD [4] — [5] — [6] NOWDALIGN_xC [7] NOWDALIGN_xD ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Reserved for future use Reserved for future use ENBYSYNC_xC= 1 Enables Receiver Byte Synchronization for Channel xC. ENBYSYNC_xC = 0 on device reset. ENBYSYNC_xD = 1 Enables Receiver Byte Synchronization for Channel xA. ENBYSYNC_xD = 0 on device reset. ...
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... XAUI_MODE[A:B] 30821 - A [0] NOCHALGN [A:B] 30921 - B [1:7] — ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Reserved for future use Reserved for future use Word Realign Bit. When DOWDALIGN_xC transitions from the receiver realigns on the next comma character for Channel xC. ...
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... B [1] SYNC2_[A:B]_OVFL [2:3] — [4] SYNC2_[A:B]_OOS [5:7] — ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use. 00 Reserved for future use. Reserved for future use. ...
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... Common Status Registers 30A03 [0] SYNC4_OVFL [1] SYNC4_OOS [2:7] — * Useful values for RX_FIFO_MIN [0:4] are 0 to 17(decimal) ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES quad Channel Channel AD Receive Clock Select. Controls source of 78 MHz RCK78 for SERDES ...
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... ORT82G5 Memory Map Each ORT82G5 SERDES block has eight independent channels. Each channel is identified by both a quad identi- fier and a channel identifier The registers in ORT82G5 are 8-bit memory locations, which can be classified into Status Register and Control Register. ...
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... BD [2] PE0_xx [3] PE1_xx [4] HAMP_xx [5] Reserved [6] Reserved [7] 8b10bT_xx ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Reserved Receive PLL Lock Indication, Channel xx. LKI_xx = 1 indicates the receive PLL is locked. Reserved Reserved Not used FF Reserved, must be set to 1. Set device reset. ...
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... SWRST_xx 30124 - BC 30134 - BD [3:6] Not used [7] TESTEN_xx ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 20 Receive Half Rate Selection Bit, Channel xx. When RXHR_xx =1, HDIN_xx's baud rate = (REFCLK[A:B]*10) and RCK78[A:B]=(REF- CLK[A:B]/4); when RXHR_xx=0, HDIN_xx's baud rate = (REF- CLK[A:B]*20) and RCK78[A:B]=(REFCLK/2). RXHR_xx = 0 on device reset ...
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... LOOPENB_xx 30901 - Bx [1]xB [2]xC [3]xD [4]xA NOWDALIGN_xx [5]xB [6]xC [7]xD ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) See Reserved, must be set to 0. Set device reset. bit Global Mask. When GMASK_[A: the transmit and receive alarms descrip. of all channels in the SERDES quad are prevented from generating an interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit over- rides the individual MASK_xx bits ...
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... XAUISTAT_xx[0:1] 30904 - Bx xA [2:3] xB [4:5] xC [6:7] xD ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Word Realign Bit. When DOWDALIGN_xx transitions from the receiver realigns on the next comma character for Channel xx. NOWDALIGN_xx=0 on device reset. Enable multi-channel alignment for Channel xx. When FMPU_STR_EN_xx=1, the corresponding channel participates in multi- channel alignment ...
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... TCKSELB [6:7] RCKSELB 30A01 [0:4] — [5:7] RX_FIFO_MIN ORCA ORT42G5 and ORT82G5 Data Sheet Reset Value (0x) 00 Status of Word Alignment. When DEMUX_WAS_xx=1, word alignment is achieved for Channel xx. DEMUX_WAS_xx=0 on device reset. Status of Channel Alignment. When CH248_SYNC_xx=1, multi-channel alignment is achieved for Channel xx. CH248_SYNC_xx=0 on device reset. ...
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... Each board that uses the ORT42G5 or ORT82G5 as a transmit or receive device will have its own local reference clock as shown in Figure 37. Figure 37 shows the ORT82G5 device on the switch card receiving data on two of its channels from a separate source. Data tx1 is transmitted from a tx device with refclk1 as the reference clock and Data tx2 is transmitted from a tx device with refclk2 as the reference clock ...
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... This may require expensive clock driver chips on the board to drive clocks to different destinations within the specified jitter limits for the reference clock. Figure 38. Distributed Reference Clock to Rx And Tx Devices ORCA ORT42G5 and ORT82G5 Data Sheet REFCLK BACKPLANE PORT CARD #1 ...
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... SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 1.25 Gbit/s SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 2.50 Gbit/s ORT42G5 Power Dissipation SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 3.125 Gbit/s 8b/10b Encoder/Decoder (per Channel) 1. With all channels operating, 1.575V supply. ORCA ORT42G5 and ORT82G5 Data Sheet Symbol Min. T – 65 STG V – ...
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... Wavecrest SIA-3000 instrument used to measure one-sigma (rms) random jitter component value. This value is multiplied provide the peak-to-peak value that corresponds to a BER Total jitter measurement performed with Wavecrest SIA-3000 at a BER of 10 cations for a detailed discussion of jitter types included in this measurement. ORCA ORT42G5 and ORT82G5 Data Sheet Min ...
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... Input level min + (input peak to peak swing)/2 ≤ common mode input voltage ≤ input level max - (input peak to peak swing)/2 3. The ORT42G5 and ORT82G5 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing first bit, then byte (character), then channel (32-bit word), and finally optional multi-channel alignment as described in TN1025. The PLL Lock Time is the time required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream ...
Page 78
... The Clock and Data Recovery (CDR) portion of the ORT42G5 and ORT82G5 SERDES receiver has the ability to filter incoming signal jitter that is below the clock recovery PLL bandwidth (about 3 MHz). The eye-mask specifica- tions of Table 37 are for jitter frequencies above the PLL bandwidth of the CDR, which is a worst case condition. When jitter occurs at frequencies below the PLL bandwidth, the receiver jitter tolerance is signifi ...
Page 79
... With multi-channel alignment, the latency is largest when the skew between channels is at the maximum that can be correctly compensated for (18 clock cycles). The latency specified in the table is for data from the channel received first. ORCA ORT42G5 and ORT82G5 Data Sheet Min. ...
Page 80
... Pins dedicated for the primary clock. Input pins on the middle of each side with differential pair- ing. P[TBLR]CLK[1:0][TC] I/O After configuration these pins are user programmable I/O, if not used for clock inputs. ORCA ORT42G5 and ORT82G5 Data Sheet Description After configuration 1 80 ...
Page 81
... MPI returned data on a read cycle. MPI_ACK I/O If not used for MPI these pins are user-programmable I/O pins after configuration. ORCA ORT42G5 and ORT82G5 Data Sheet Description MPI data transfer strobe status indication, a high indicates mode this is driven low indicating the MPI received the data on the write cycle or ...
Page 82
... I/O After configuration, TESTCFG is a user programmable I/O pin. 1. The FPGA States of Operation section in the ORCA Series 4 FPGAs data sheet (ORT82G5 only) contains more information on how to con- trol these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simulta- neous release of all other confi ...
Page 83
... SERDES quad A and B Pins HDOUTN_AA (ORT82G5 only) HDOUTP_AA (ORT82G5 only) HDOUTN_AB (ORT82G5 only) ORCA ORT42G5 and ORT82G5 Data Sheet I/O I Active low reset for the embedded core. All non-SERDES specific registers (addresses 308***, 309***, 30A***) in the embedded core are not reset. ...
Page 84
... V GB_B DD V _ANA DD 1. Should be externally connected on board to 3.3V pull-up resistor. ORCA ORT42G5 and ORT82G5 Data Sheet I/O O High-speed CML transmit data output – SERDES quad A, channel B. O High-speed CML transmit data output – SERDES quad A, channel C. O High-speed CML transmit data output – SERDES quad A, channel C. ...
Page 85
... Power Supplies for ORT42G5 AND ORT82G5 Power Supply Descriptions Table shows the ORT42G5 and ORT82G5 FPGA and embedded core power supply groupings. VDD33 Is a 3.3V positive power supply used for 3.3V configuration RAMs and internal PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on the board for proper operation. The fi ...
Page 86
... ANA – Tx analog power pins, Rx analog power pins, guard band power pins. DD Figure 40. Power Supply Filtering SOURCE SUPPLY_1.5 V 0.1 μf SUPPLY_V Analog DD 0.1 μf SUPPLY_V IB DD 0.1 μf SUPPLY_V OB DD 0.1 μf ORCA ORT42G5 and ORT82G5 Data Sheet 4.7 μH 1 μf 0.01 μf 10 μf 4.7 μH 1 μf 10 μf 0.01 μf 4.7 μH 1 μf 0.01 μf 10 μf 4.7 μH 1 μf 10 μf 0.01 μf 86 ...
Page 87
... No connect Total package pins Table 44 and Table 45 provide the package pin and pin function for the ORT42G5 and ORT82G5 FPSC and pack- ages. The bond pad name is identified in the PIO nomenclature used in the ispLEVER System software design edi- tor. The Bank column provides information as to which output voltage level bank the given pin is in. The Group column provides information as to the group of pins the given pin is in ...
Page 88
... J4 7 (CL (CL (CL (CL (CL (CL (CL (CL (CL (CL (CL ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description - O PRD_DATA - VDD15 VDD15 - I PRESET_N - I PRD_CFG_N - I PPRGRM_N 7 IO PL2D 7 IO PL2C 7 IO PL3C - VSS VSS 7 ...
Page 89
... T1 6 (BL (BL (BL (BL (BL (BL) G13 - W2 6 (BL (BL (BL (BL F13 - ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description - VSS VSS 5 IO PL21D 5 IO PL21C 5 IO PL22D - VDD15 VDD15 - VSS VSS 6 IO PL24D 6 IO PL24C ...
Page 90
... H11 - V7 6 (BL (BL) AA7 6 (BL) AB7 6 (BL (BL) H12 - W8 6 (BL (BL (BL) AA8 6 (BL) AB8 6 (BL) ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description - IO LVDS_R - VDD33 VDD33 - VDD15 VDD15 5 IO PB2A 5 IO PB2C 5 IO PB2D 5 IO PB4A 5 IO ...
Page 91
... AB14 5 (BC) AA14 5 (BC Y13 5 (BC) W13 5 (BC) U15 5 (BC) AB15 5 (BC) AA15 5 (BC) AB16 5 (BC) AA16 5 (BC) H14 - ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description 1 IO PB17A 1 IO PB17C 1 IO PB17D 1 IO PB18A 1 IO PB18C 1 IO PB18D - VDD15 ...
Page 92
... W22 - F18 - V21 - V22 - U21 - U22 - E20 - G17 - G18 - J16 - J17 - T20 - J18 - T21 - F19 - ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description 6 IO PB29C 6 IO PB29D - VSS VSS 7 IO PB30C 7 IO PB30D - VDDIO5 VDDIO5 7 IO PB31C 7 IO PB31D - VDDIO5 VDDIO5 ...
Page 93
... L21 - L20 - N16 - L19 - N17 - K22 - M16 - K21 - N18 - K20 - M17 - J20 - J21 - M18 - J22 - H20 - ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description - I HDINP_BC - VDD_ANA VDD_ANA - VSS VSS - VDD_ANA VDD_ANA - VDDOB VDDOB_BC - O HDOUTN_BC - VSS VSS - O HDOUTP_BC - VDDOB VDDOB_BC - VSS VSS ...
Page 94
... K11 - D17 - M7 - C21 - C22 - K12 - E16 - M15 - C17 - D16 1 (TC) C16 1 (TC) F14 1 (TC) F15 1 (TC) E14 1 (TC) ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description - VDD_ANA VDD_ANA - VSS VSS - VDD_ANA VDD_ANA - I HDINP_AC - VSS VSS - I HDINN_AC - VDD_ANA VDD_ANA - VDDIB VDDIB_AC - VDD_ANA ...
Page 95
... B15 1 (TC) F16 1 (TC) E11 1 (TC) L10 - D11 1 (TC) C11 1 (TC) A14 1 (TC) B14 1 (TC) A13 1 (TC) B13 1 (TC) G14 1 (TC) ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description 8 IO PT34B 8 IO PT33D 8 IO PT33C - VDDIO1 VDDIO1 8 IO PT32D 8 IO PT32C - ...
Page 96
... C6 0 (TL (TL (TL (TL (TL (TL (TL (TL) E10 0 (TL) B22 - C4 0 (TL) ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description - VSS VSS - VDD15 VDD15 5 IO PT18D 5 IO PT18C 5 IO PT17D 5 IO PT17C - VDD15 VDD15 5 IO PT16D ...
Page 97
... W17 5 (BC) W18 5 (BC (CL (CL U17 - V5 - V18 - R18 - R19 - T19 - U19 - U20 - V19 - V20 - W20 - ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description 6 IO PT2C - O PCFG_MPI_IRQ - IO PCCLK - VDD15 VDD15 - IO PDONE - VDD33 VDD33 - VDD15 VDD15 - VDD15 VDD15 - VDD15 VDD15 - VDD15 ...
Page 98
... R10 - R11 - R12 - R13 - R14 - AA1 - AA19 - AA20 - AA21 - AA22 - AB1 - AB19 - AB20 - AB21 - AB22 - ORCA ORT42G5 and ORT82G5 Data Sheet I/O Pin Description - VSS VSS - VSS VSS - VSS VSS - VSS VSS - VSS VSS - VSS VSS - VSS VSS - VSS VSS - VSS VSS ...
Page 99
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout 680-PBGAM V IO Bank VREF Group DD AB20 — — C3 — — E4 — — F5 — — G5 — — D3 — — (TL) — (TL (TL (TL) — (TL (TL — — (TL) ...
Page 100
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD AA15 — — (TL (CL (CL) 1 AA3 7 (CL) — (CL (CL (CL (CL) 1 V18 — — (CL (CL) ...
Page 101
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD W18 — — (CL (CL) 5 W19 — — (CL (CL (CL (CL (CL (CL (CL) 5 AA1 7 (CL) 5 Y13 — ...
Page 102
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD Y20 — — AG2 7 (CL) 8 AH1 7 (CL) 8 AF3 6 (BL) 1 AG3 6 (BL) 1 AL7 6 (BL) — AE4 6 (BL) 1 AF4 6 (BL) 1 AE5 6 (BL) 1 AF5 6 (BL) 1 R21 — — AJ1 6 (BL) ...
Page 103
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD AM4 6 (BL) 5 AL5 6 (BL) 5 AN7 6 (BL) — AP3 6 (BL) 5 AP4 6 (BL) 5 AN4 6 (BL) 5 U16 — — AK6 6 (BL) 5 AK7 6 (BL) 5 AL6 6 (BL) 5 AM6 6 (BL) 5 AP1 6 (BL) — ...
Page 104
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD AM12 6 (BL) 9 AP12 6 (BL) 9 AP13 6 (BL) 9 AM13 6 (BL) 9 AN14 6 (BL) 9 V17 — — AP14 6 (BL) 10 AP15 6 (BL) 10 AK13 6 (BL) 10 AK14 6 (BL) 10 AM14 6 (BL) 10 AL14 6 (BL) 10 AP17 6 (BL) ...
Page 105
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD AL19 5 (BC) 3 AK18 5 (BC) 3 P15 — — AP24 5 (BC) 3 AN23 5 (BC) 3 AP25 5 (BC) 3 AP26 5 (BC) 3 AL13 5 (BC) — AL20 5 (BC) 3 AK19 5 (BC) 3 AK20 5 (BC) 3 AL21 5 (BC) 3 P20 — ...
Page 106
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD AM28 5 (BC) 7 AN30 5 (BC) 7 R14 — — AK25 5 (BC) 7 AL26 5 (BC) 7 AN17 5 (BC) — AL27 5 (BC) 8 AL28 5 (BC) 8 AN31 5 (BC) 8 R15 — — AK26 5 (BC) 8 AM30 5 (BC) ...
Page 107
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD AA32 — — AF30 — — AF31 — — AE30 — — AE31 — — AB32 — — AD30 — — AD32 — — AF33 — — ...
Page 108
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD W31 — — V30 — — W33 — — H33 — — W34 — — V31 — — H34 — — J32 — — U31 — — ...
Page 109
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD P32 — — J34 — — J33 — — R32 — — L30 — — K31 — — K30 — — J31 — — J30 — — ...
Page 110
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD B29 1 (TC) 8 C29 1 (TC) 8 B15 1 (TC) — E27 1 (TC) 8 E26 1 (TC) 8 AP34 — — A30 1 (TC) 8 A29 1 (TC) 9 E25 1 (TC) 9 B17 1 (TC) — E24 1 (TC) 9 B28 1 (TC) ...
Page 111
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD B24 1 (TC) 3 D20 1 (TC) 3 D19 1 (TC) 3 N14 — — E19 1 (TC) 3 E18 1 (TC) 3 C21 1 (TC) 4 C20 1 (TC) 4 A25 1 (TC) 4 A24 1 (TC) 4 B23 1 (TC) 4 A23 1 (TC) 4 N15 — ...
Page 112
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group (TL) — C14 0 (TL) 1 B14 0 (TL) 1 A14 0 (TL) 1 A13 0 (TL) 1 AA20 — — E12 0 (TL) 2 E13 0 (TL) 2 C13 0 (TL) 2 C12 0 (TL) 2 B12 0 (TL) 2 A12 0 (TL) 2 D12 ...
Page 113
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group (TL (TL (TL (TL — — E6 — — D4 — — E5 — — AB15 — — AL33 — — AL34 — — AM34 — ...
Page 114
... Lattice Semiconductor Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued) 680-PBGAM V IO Bank VREF Group DD U21 — — U22 — — V13 — — V14 — — V15 — — V20 — — V21 — — V22 — — W13 — — ...
Page 115
... Management section of the Lattice web site at www.latticesemi.com. Heat Sink Vendors for BGA Packages The estimated worst-case power requirements for the ORT42G5 and ORT82G5 are in the range. Con- sequently, for most applications an external heat sink will be required. Table 46 lists, in alphabetical order, heat sink vendors who advertise heat sinks aimed at the BGA market ...
Page 116
... Package Outline Drawings Package Outline Drawings for the 484-ball PBGAM (fpBGA) used for the ORT42G5 and 680-ball PBGAM (fpBGA) used for the ORT82G5 are available in the Package Diagrams section of the Lattice Semiconductor web site at www.latticesemi.com. ORCA ORT42G5 and ORT82G5 Data Sheet ...
Page 117
... ORT82G5-3BM680C2 ORT82G5-2BM680C ORT82G5-1BM680C 1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade ...
Page 118
... For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster. 2. Refer to the Thermal Management document at www.latticesemi.com for Θ ORCA ORT42G5 and ORT82G5 Data Sheet 1 Industrial ...
Page 119
... Lattice Semiconductor Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version — — Previous Lattice releases. July 2008 07.0 BM680 conversion to F680 per PCN#09A-08. ORCA ORT42G5 and ORT82G5 Data Sheet Change Summary 119 ...