ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 68

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Table 30. ORT82G5 Memory Map
Lattice Semiconductor
SERDES Alarm Registers (Read Only), xx=[AA,...,BD]
30000 - AA
30010 - AB
30020 - AC
30030 - AD
30100 - BA
30110 - BB
30120 - BC
30130 - BD
SERDES Alarm Mask Registers (Read/Write), xx=[AA,...,BD]
30001 - AA
30011 - AB
30021 - AC
30031 - AD
30101 - BA
30111 - BB
30121 - BC
30131 - BD
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), xx=[AA,...,BD]
30002 - AA
30012 - AB
30022 - AC
30032 - AD
30102 - BA
30112 - BB
30122 - BC
30132 - BD
Absolute
Address
(0x)
[4:7]
Bit
[0]
[1]
[2]
[3]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Reserved
LKI_xx
Reserved
Reserved
Not used
Reserved
MLKI_xx
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TXHR_xx
PWRDNT_xx
PE0_xx
PE1_xx
HAMP_xx
Reserved
Reserved
8b10bT_xx
Name
Reset
Value
(0x)
FF
00
00
Reserved
Receive PLL Lock Indication, Channel xx. LKI_xx = 1 indicates the
receive PLL is locked.
Reserved
Reserved
Not used
Reserved, must be set to 1. Set to 1 on device reset.
Mask Receive PLL Lock Indication, Channel xx.
Reserved, must be set to 1. Set to 1 on device reset.
Reserved, must be set to 1. Set to 1 on device reset.
Reserved, must be set to 1. Set to 1 on device reset.
Reserved, must be set to 1. Set to 1 on device reset.
Reserved, must be set to 1. Set to 1 on device reset.
Reserved, must be set to 1. Set to 1 on device reset.
Transmit Half Rate Selection Bit, Channel xx. When TXHR_xx = 1,
HDOUT_xx's baud rate = (REFCLK[A:B]*10) and TCK78[A:B] =(REF-
CLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's baud rate = (REF-
CLK[A:B]*20) and TCK78[A:B]=(REFCLK[A:B]/2). TXHR_xx = 0 on
device reset.
Transmit Powerdown Control Bit, Channel xx. When PWRDNT_xx = 1,
sections of the transmit hardware are powered down to conserve power.
PWRDNT_xx = 0 on device reset.
Transmit Preemphasis Selection Bit 0, Channel xx. PE0_xx and PE1_xx
select one of three preemphasis settings for the transmit section.
PEO_xx=PE1_xx = 0, Preemphasis is 0%
PEO_xx=1, PE1_xx = 0 or PEO_xx=0, PE1_xx = 1, Preemphasis is
12.5%
PEO_xx=PE1_xx = 1, Preemphasis is 25%.
PEO_xx=PE1_xx = 0 on device reset.
Transmit Half Amplitude Selection Bit, Channel xx. When HAMP_xx = 1,
the transmit output buffer voltage swing is limited to half its normal ampli-
tude. Otherwise, the transmit output buffer maintains its full voltage
swing. HAMP_xx = 0 on device reset.
Reserved. Must be set to 0. Set to 0 on device reset.
Reserved
Transmit 8b/10b Encoder Enable Bit, Channel xx. When 8b10bT_xx = 1,
the 8b/10b encoder in the transmit path is enabled. Otherwise, the data
is passed unencoded. 8b10bT_xx = 0 on device reset.
68
ORCA ORT42G5 and ORT82G5 Data Sheet
Description