ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 10

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
System Bus
An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration
logic, FPGA control, status registers, Embedded Block RAMs, as well as user logic. Utilizing the AMBA specifica-
tion Rev 2.0 AHB protocol, the Embedded System Bus offers arbiter, decoder, master, and slave elements. Master
and slave elements are also available for the user-logic and a slave interface is used for control and status of the
embedded backplane transceiver portion of the device.
The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset func-
tions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is
integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the micro-
processor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from
routing, or from the port clock (for JTAG configuration modes).
Phase-Locked Loops
Up to eight PLLs are provided on each Series 4 device, with four user PLLs generally provided for FPSCs. Pro-
grammable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Each PPLL is
capable of manipulating and conditioning clocks from 20 MHz to 200 MHz. Frequencies can be adjusted from 1/8x
to 8x, the input clock frequency. Each programmable PLL provides two outputs that have different multiplication fac-
tors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the
clock period increments. An automatic input buffer delay compensation mode is available for phase delay. Each
PPLL provides two outputs that can have programmable (12.5% steps) phase differences.
Embedded Block RAM
New 512 x 18 block-port RAM blocks are embedded in the FPGA core to significantly increase the amount of mem-
ory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two
byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available,
as well as direct connection to the high-speed system bus.
Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable
multiply functions. The user can configure FIFO blocks with flexible depths of 512K, 256K, and 1K including asyn-
chronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple
of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiple of two 8-bit numbers (16-
bit output). On-the-fly coefficient modifications are available through the second read/write port.
Two 16 x 8-bit CAMs per embedded block can be implemented in single match, multiple match, and clear modes.
The EBRs can also be preloaded at device configuration time.
Configuration
The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/configura-
tion circuitry loads the configuration data at power up or under system control. The configuration data can reside
externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for
configuring FPGAs.
The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial,
master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface
and Embedded System Bus to perform both programming and readback. Daisy chaining of multiple devices and
partial reconfiguration are also permitted.
Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as
well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE
1149.2) port is also available meeting In-System Programming (ISP™) standards (IEEE 1532 Draft).
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