ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 38

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
data rate and bit-width so the FPGA core can run at 1/4th this frequency which gives a range of 15 to 92.5 MHz for
the data in and out of the FPGA.
Internal Clock Signals at the FPGA/Core Interface for the ORT42G5
There are several clock signals defined at the FPGA/Embedded Core interface in addition to the external reference
clock for each SERDES block. All of the ORT42G5 clock signals are shown in Figure 17 and are described follow-
ing the figure.
Figure 17. ORT42G5 Clock Signals (High Speed Serial I/O Also Shown)
REFCLKP_[A:B], REFCLKN_[A:B]:
These are the differential reference clocks provided to the ORT42G5 device as described earlier. They are used as
the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbps, the reference clocks
will be at a frequency of 156.25 MHz.
RWCK[AC, AD, BC, BD]:
These are the low-speed receive clocks from the embedded core to the FPGA across the core-FPGA interface.
These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCKAC
belongs to Channel AC, RWCKBC belongs to channel BC and so on. With a reference clock input of 156.25 MHz,
these clocks operate at 78.125 MHz.
RCK78[A:B]:
These are muxed outputs of RWCKA[C or D] and RWCKB[C or D] respectively. With a reference clock input of
156.25 MHz, these clocks operate at 78.125 MHz.
RSYS_CLK_[A:B]2
These clocks are inputs to the SERDES blocks A and B respectively from the FPGA. These are used by each
channel as the read clock to read received data from the alignment FIFO within the embedded core. Clock
RSYS_CLK_A2 is used by channels in the SERDES block A and RSYS_CLK_B2 by channels in the SERDES
block B. To guarantee that there is no overflow in the alignment FIFO, it is an absolute requirement that the write
and read clocks be frequency locked within 0 ppm. Examples of how to achieve this are shown in the later section
on recommended board-level clocking.
FPGA
Logic
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
TSYS_CLK_BC
RSYS_CLK_B2
TSYS_CLK_BD
RWCKAC
RCK78A
TCK78A
TCK78A
RWCKAC
RWCKBD
RWCKBC
RCK78B
TCK78B
Common Logic, Block A
Common Logic, Block B
Channel AC
Channel AD
Channel BC
Channel BD
38
ORCA ORT42G5 and ORT82G5 Data Sheet
2
2
2
2
2
2
2
2
2
2
REFCLK[P:N]_A
HDIN[P:N]_AC
HDOUT[P:N]_AC
HDOUT[P:N]_AD
HDIN[P:N]_AD
HDIN[P:N]_BD
HDOUT[P:N]_BD
REFCLK[P:N]_B
HDIN[P:N]_BC
HDOUT[P:N]_BC
Backplane
Serial
Link