ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 80

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor. If any pin
is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor after configuration.
The pin descriptions in Table and throughout this data sheet show active-low signals with an overscore. The pack-
age pinout tables that follow, show this as a signal ending with _N. For example LDC and LDC_N are equivalent.
Table 40. Pin Descriptions
Dedicated Pins
V
V
V
V
PTEMP
RESET
CCLK
DONE
PRGRM
RD_CFG
RD_DATA/TDO
CFG_IRQ/MPI_IRQ
LVDS_R
Special-Purpose Pins
M[3:0]
PLL_CK[0:7][TC]
P[TBLR]CLK[1:0][TC]
DD
DD
DD
SS
33
15
IO
Symbol
I/O
I/O After configuration, these pins are user-programmable I/O.
I/O These pins are user-programmable I/O pins if not used by PLLs after configuration.
I/O After configuration these pins are user programmable I/O, if not used for clock inputs.
— 3.3V positive power supply. This power supply is used for 3.3V configuration RAMs and internal
— 1.5V positive power supply for internal logic.
— Positive power supply used by I/O banks.
— Ground.
— Reference resistor connection for controlled impedance termination of Series 4 FPGA LVDS
O In the master and asynchronous peripheral modes, CCLK is an output which strobes configura-
O As an active-high, open-drain output, a high level on this signal indicates that configuration is
O RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration
O During JTAG, slave, master, and asynchronous peripheral configuration assertion on this
I
I
I
I
I
I
I
I
I
PLLs. When using PLLs, this power supply should be well isolated from all other power supplies
on the board for proper operation.
Temperature sensing diode pin. Dedicated input.
During configuration, RESET forces the restart of configuration and a pull-up is enabled. After
configuration, RESET can be used as a general FPGA input or as a direct input, which causes
all PLC latches/FFs to be asynchronously set/reset.
tion data in.
D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, periph-
eral, or system bus modes.
As an input, a low level on DONE delays FPGA start-up after configuration.
complete. DONE has an optional pull-up resistor.
PRGRM is an active-low input that forces the restart of configuration and resets the boundary-
scan circuitry. This pin always has an active pull-up.
This pin must be held high during device initialization until the INIT pin goes high. This pin
always has an active pull-up. During configuration, RD_CFG is an active-low input that activates
the TS_ALL function and 3-states all of the I/O.
(via a bit stream option) to activate the TS_ALL function as described above, or, if readback is
enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the
configuration data, including PFU output states, starting with frame address 0.
data out. If used in boundary-scan, TDO is test data out.
CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization.
active-low interrupt request output, when the MPI is used.
inputs.
During powerup and initialization, M0—M3 are used to select the configuration mode with their
values latched on the rising edge of INIT . During configuration, a pull-up is enabled.
Semi-dedicated PLL clock pins. During configuration they are 3-stated with a pull up.
Pins dedicated for the primary clock. Input pins on the middle of each side with differential pair-
ing.
In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or
80
ORCA ORT42G5 and ORT82G5 Data Sheet
Description
After configuration
1
, RD_CFG can be selected
1
MPI