ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 64

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
30810 - Ax
30910 - Bx
30811 - Ax
30911 - Bx
30820 - Ax
30920 - Bx
30821 - A
30921 - B
Absolute
Address
(0x)
[0:7] FMPU_SYNMODE_
[1:7]
Bit
[0]]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
DOWDALIGN_xC
FMPU_STR_EN _xC
FMPU_STR_EN _xD
[A:B]
FMPU_RESYNC1_xC
FMPU_RESYNC1_xD
FMPU_RESYNC2[A:B]
XAUI_MODE[A:B]
NOCHALGN [A:B]
DOWDALIGN_xC
Name
—
—
—
—
—
—
—
—
—
Reset
Value
(0x)
00
00
00
00
Word Realign Bit. When DOWDALIGN_xC transitions from 0 to 1, the
receiver realigns on the next comma character for Channel xC.
NOWDALIGN_xC=0 on device reset.
Word Realign Bit. When DOWDALIGN_xC transitions from 0 to 1, the
receiver realigns on the next comma character for Channel xC.
NOWDALIGN_xC=0 on device reset.
Enable multi-channel alignment for Channel xC.
When FMPU_STR_EN _xC = 0, Channel xC is not part of a multi-chan-
nel alignment group
When FMPU_STR_EN _xC = 1, Channel xC is part of a twin channel
alignment (SERDES block A or B) or quad channel alignment (both
SERDES blocks) group.
Enable multi-channel alignment for Channel xD.
When FMPU_STR_EN _xD = 0, Channel xD is not part of a multi-chan-
nel alignment group
When FMPU_STR_EN _xD = 1, Channel xD is part of a twin channel
alignment (SERDES block A or B) or quad channel alignment (both
SERDES blocks) group.
Sync mode for block [A:B]
00000000 = No channel alignment
00001010 = Twin channel alignment, SERDES block [A:B]
00001111 = Quad channel alignment (both SERDES blocks)
Resync a Single Channel. When FMPU_RESYNC1_xC transitions from
0 to 1, the corresponding channel xC is resynchronized (the write and
read pointers are reset). FMPU_STR_EN_xC=0 on device reset.
Resync a Single Channel. When FMPU_RESYNC1_xD transitions from
0 to 1, the corresponding channel xD is resynchronized (the write and
read pointers are reset). FMPU_STR_EN_xD=0 on device reset.
Resync a Twin-Channel Group. When FMPU_RESYNC2[A:B] transitions
from a 0 to a 1, the corresponding twin-channel group is resynchronized.
FMPU_RESYNC2[A:B]=0 on device reset.
Controls use of XAUI link state machine in place of Fibre-Channel state
machine. When XAUI_MODE[A:B]=1, both channels in the SERDES
block enable their XAUI link state machines. (LINKSM_xx bits are
ignored). XAUI_MODE[A:B]=0 on device reset.
Bypass channel alignment. NOCHALGN [A:B] =1 causes bypassing of
multi-channel alignment FIFOs for the corresponding SERDES quad.
NOCHALGN [A:B] =0 on device reset.
64
ORCA ORT42G5 and ORT82G5 Data Sheet
Reserved for future use. Set to zero.
Reserved for future use. Set to zero.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use
Reserved for future use
Description