ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 12

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
The transceivers are controlled and configured through the system bus in the FPGA logic and through the external
8-bit microprocessor interface of the FPGA. Each channel has associated dedicated registers that are readable
and writable. There are also global registers for control of common circuitry and functions.
The SERDES performs 8b/10b encoding and decoding for each channel. The 8b/10b transmission code can sup-
port either Ethernet or Fibre Channel specifications for serial encoding/decoding, special characters, and error
detection.
The user can disable the 8b/10b decoder to receive raw 10-bit words which will be rate reduced by the SERDES. If
this mode is chosen, the user must bypass the multi-channel alignment FIFOs.
The SERDES block contains its own dedicated PLLs for both transmit and receive clock generation. The user pro-
vides a reference clock of the appropriate frequency. The receiver PLLs extract the clock from the serial input data
and retime the data with the recovered clock.
MUX/DEMUX Block
The MUX/DEMUX block converts the data format for the high speed serial links to a wide, low-speed format for
crossing the CORE/FPGA interface. The intermediate interface to the SERDES macrocell runs at 1/10th the bit
rate of the data lane. The MUX/DEMUX converts the data rate and bus width so the interface to the FPGA core can
run at 1/4th this intermediate frequency, giving a range of 25.0-92.5 MHz for the data rates into and out of the
FPGA logic.
Multi-channel Alignment FIFOs
In the ORT82G5, the eight incoming data channels (four per SERDES block) can be independent of each other or
can be synchronized in several ways. Two channels within a SERDES block can be aligned together; channels A
and B and/or channels C and D. Alternatively, four channels in a SERDES block can be aligned together to form a
communication channel with a bandwidth of 10 Gbps. Finally, the alignment can be extended across both SERDES
blocks to align all eight channels. Individual channels within an alignment group can be disabled (i.e., powered
down) without disrupting other channels.
In the ORT42G5, the four incoming data channels (two per SERDES block) can be independent of each other or
can be synchronized in two ways. Two channels, channels C and D, within either SERDES block can be aligned
together. Alternatively, all four channels can be aligned together to form a communication channel with a bandwidth
of 10 Gbps. Individual channels within an alignment group can be disabled (i.e., powered down) without disrupting
other channels.
XAUI and Fibre Channel Link State Machines
Two separate link state machines are included in the architecture. A XAUI link state machine is included in the
embedded core modeled after the IEEE 802.3ae standard. A separate state machine for Fibre Channel is also
implemented.
FPGA/Embedded Core Interface
In 8b/10b mode, the FPGA logic will receive/transmit 32-bits of data (up to 92.5 MHz) and 4 K_CTRL bits from/to
the embedded core. There are 8 data streams in each direction plus additional timing, status and control signals.
Data sent to the FPGA can be aligned using comma (/K/) characters or /A/ character as specified either by Fibre
Channel or by IEEE 802.3ae for XAUI based interfaces. The alignment character is made available to the FPGA
along with the data. The special characters K28.1, K28.5 and K28.7 are treated as valid comma characters by the
SERDES.
If the receive channel alignment FIFOs are bypassed, then each channel will provide its own receive clock in addi-
tion to data and comma character detect signals. If the 8b/10b decoders are bypassed, then 40-bit data streams
are passed to the FPGA logic. No channel alignment can be done in 8b/10b bypass mode.
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