ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 7

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
Description
What is an FPSC?
FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or
mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the
design effort savings of using soft Intellectual Property (IP) cores, and the speed, design density, and economy of
ASICs.
FPSC Overview
Lattice’s Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of
Programmable Logic Cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded
logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the
FPGA functionality is changed—all of the Series 4 FPGA capability is retained including: the Embedded Block
RAMs, MicroProcessor Interface (MPI), boundary scan, etc. The columns of programmable logic are replaced at
the right of the device, allowing pins from the replaced columns to be used as I/O pins for the embedded core. The
remainder of the device pins retain their FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.
Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count
is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-
area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and
accounted for in the Lattice ispLEVER™ System software.
Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-master
32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic func-
tions including the Embedded Block RAMs and the microprocessor interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This
allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embed-
ded core configurations may be designed into a single device with user-programmable control over which configu-
rations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER System software and third-party
synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC
implementation. Included in the kit are the FPSC configuration manager, complied Verilog simulation models,
HSPICE and/or IBIS models for I/O buffers, and complete online documentation. The kit's software coupled with
the design environment, provides a seamless FPSC design environment. More information can be obtained by vis-
iting the Lattice web site at www.latticesemi.com or contacting a local sales office.
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