XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 81

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 54: Serial Peripheral Interface (SPI) Connections (Continued)
Voltage Compatibility
Available SPI Flash PROMs use a single 3.3V supply volt-
age. All of the FPGA’s SPI Flash interface signals are within
I/O Bank 2. Consequently, the FPGA’s VCCO_2 supply
voltage must also be 3.3V to match the SPI Flash PROM.
Power-On Precautions if 3.3V Supply is Last in
Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in
Table 55: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
DS312-2 (v3.4) November 9, 2006
Product Specification
INIT_B
DONE
PROG_B
STMicroelectronics
Spansion
NexFlash
Macronix
Silicon Storage Technology
Programmable
Microelectronics Corporation
Atmel Corporation
Pin Name
Vendor
R
bidirectional
bidirectional
Open-drain
Open-drain
Direction
FPGA
Input
I/O
I/O
Figure
66. The FPGA waits for its three
Initialization Indicator. Active Low.
Goes Low at start of configuration during
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
FPGA Configuration Done. Low during
configuration. Goes High when FPGA
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
Program FPGA. Active Low. When
asserted Low for 300 ns or longer, forces
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns
High. Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving externally with
a 3.3V output, use an open-drain or
open-collector driver or use a current
limiting series resistor.
SPI Flash PROM
Part Number
AT45DBxxxD
AT45DBxxxB
SST25LFxx
Pm25LVxxx
S25FLxxxA
MX25Lxxxx
M25Pxx
Description
NX25xx
www.xilinx.com
Data Sheet Minimum Time from V
power supplies
(VCCO_2)
before beginning the configuration process.
The SPI Flash PROM is powered by the same voltage sup-
ply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
accessed until their V
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table
T
Symbol
PU-READ
Active during configuration. If
SPI Flash PROM requires > 2
ms to awake after powering on,
hold INIT_B Low until PROM is
ready. If CRC error detected
during configuration, FPGA
drives INIT_B Low.
Low indicates that the FPGA is
not yet configured.
Must be High to allow
configuration to start.
t
T
T
T
t
VCSL
t
VSL
VCS
VSL
PU
VSL
55. For other vendors, this delay is as much as 20 ms.
During Configuration
—
to reach their respective power-on thresholds
—
V
CCINT
CC
Value
supply reaches its minimum data
, V
10
10
10
10
10
50
30
20
CCAUX
CC
User I/O. If unused in the
application, drive INIT_B
High.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to SPI
Flash PROM pins.
Functional Description
, and V
min to Select = Low
After Configuration
CCO
to I/O Bank 2
Units
ms
ms
μs
μs
μs
μs
μs
μs
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