XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 109

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
DS312-2 (v3.4) November 9, 2006
Product Specification
UnusedPin
DONE_cycle
GWE_cycle
GTS_cycle
LCK_cycle
DonePin
DriveDone
DonePipe
Option Name
R
Pins/Function
shift registers,
Configuration
Configuration
Configuration
Configuration
All flip-flops,
Block RAM,
LUT RAMs,
All I/O pins,
Unused I/O
and SRL16
DONE pin,
DONE pin
DONE pin
DONE pin
Affected
Startup
Startup
Startup
DCMs,
Pins
Pulldown
1, 2, 3, 4,
1, 2, 3, 4,
1, 2, 3, 4,
0, 1, 2, 3,
(default)
Pullnone
Pullnone
NoWait
Values
Pullup
Pullup
4, 5, 6
Done
Keep
Done
Keep
5, 6
5, 6
5, 6
Yes
Yes
No
No
Default. All unused I/O pins and input-only pins have a pull-down resistor to GND.
All unused I/O pins and input-only pins have a pull-up resistor to the VCCO_# supply
for its associated I/O bank.
All unused I/O pins and input-only pins are left floating (Hi-Z, high-impedance,
three-state). Use external pull-up or pull-down resistors or logic to apply a valid signal
level.
Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
Start-Up.
Selects the Configuration Startup phase that asserts the internal write-enable signal to
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read
and write operations. See Start-Up.
Waits for the DONE pin input to go High before asserting the internal write-enable
signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and
write operations are enabled at this time.
Retains the current GWE_cycle setting for partial reconfiguration applications.
Selects the Configuration Startup phase that releases the internal three-state control,
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See Start-Up.
Waits for the DONE pin input to go High before releasing the internal three-state
control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive,
if so configured, after this point.
Retains the current GTS_cycle setting for partial reconfiguration applications.
The FPGA does not wait for selected DCMs to lock before completing configuration.
If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,
the FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
Internally connects a pull-up resistor between DONE pin and V
330 Ω pull-up resistor to V
No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to V
is required.
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to V
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
The input path from DONE pin input back to the Startup sequencer is not pipelined.
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
www.xilinx.com
CCAUX
is still recommended.
CCAUX
Description
for a valid logic High.
Functional Description
CCAUX
. An external
CCAUX
109