XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 58

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
The eight bits of the STATUS bus are described in
Table 37: Status Logic Signals
Table 38: DCM Status Bus
58
Notes:
1.
RST
STATUS[7:0]
LOCKED
3-6
Bit
0
1
2
When only the DFS clock outputs but none of the DLL clock outputs are used, this bit does not go High when the CLKIN signal stops.
Signal
Reserved
CLKIN Stopped
CLKFX Stopped
Reserved
Name
Input
Output
Output
Direction
-
When High, indicates that the CLKIN input signal is not toggling. When Low, indicates CLKIN
is toggling. This bit functions only when the CLKFB input is connected.
When High, indicates that the CLKFX output is not toggling. When Low, indicates the CLKFX
output is toggling. This bit functions only when the CLKFX or CLKFX180 output are connected.
-
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for
a delay of zero. Sets the LOCKED output Low. This input is asynchronous.
The bit values on the STATUS bus provide information regarding the state of DLL and
PS operation
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two
signals are out-of-phase when Low.
Table
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38.
Description
Description
DS312-2 (v3.4) November 9, 2006
(1)
Product Specification
R