XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 140
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XC3S100E-4CP132GI
Manufacturer Part Number
XC3S100E-4CP132GI
Description
Spartan-3E FPGA Family: Complete Data Sheet
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
1.XC3S100E-4CP132GI.pdf
(231 pages)
- Current page: 140 of 231
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DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 100: Clock Distribution Switching Characteristics
140
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to
I0 and I1 inputs. Same as BUFGCE enable CE-input
Frequency of signals distributed on global buffers (all sides)
Description
www.xilinx.com
Symbol
F
T
T
BUFG
GIO
GSI
Minimum
-0
0
-
-
Speed Grade
DS312-3 (v3.4) November 9, 2006
1.46
0.55
333
-5
Maximum
Product Specification
1.46
0.63
311
-4
Units
MHz
ns
ns
R
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