XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 159

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Revision History
The following table shows the revision history for this document.
DS312-3 (v3.4) November 9, 2006
Product Specification
03/01/05
11/23/05
03/22/06
04/07/06
05/19/06
05/30/06
11/09/06
Date
R
Version
3.2.1
1.0
2.0
3.0
3.1
3.2
3.4
Initial Xilinx release.
Added AC timing information and additional DC specifications.
Upgraded data sheet status to Preliminary. Finalized production timing parameters. All
speed grades for all Spartan-3E FPGAs are now Production status using the v1.21 speed
files, as shown in
and clock-to-output timing based on final characterization, shown in
system-synchronous input setup and hold times based on final characterization, shown in
Table 86
adjustments for LVPECL_25, DIFF_SSTL and DIFF_HSTL I/O standards that supersede
the v1.21 speed file values, in
delays in
slice flip-flop timing by 100 ps in
SRL16 timing in
in
remainder of Step 0 device; added improved Step 1 DCM performance to
Table
T
Table
Table
MultiBoot timing specifications to
Improved SSO limits for LVDS_25, MINI_LVDS_25, and RSDS_25 I/O standards in the QFP
packages
Clarified that 100 mV of hysteresis applies to LVCMOS33 and LVCMOS25 I/O standards
(Note 4,
Corrected various typos and incorrect links.
Improved absolute maximum voltage specifications in
overshoot allowance. Widened the recommended voltage range for PCI and PCI-X
standards in
v1.26 speed file. Added
time all devices became Production status. Added absolute minimum values for
Table
IFD_DELAY_VALUE settings in
source-synchronous input capture sample window. Promoted Module 3 to Production
status. Synchronized all modules to v3.4.
INIT
Table
, in
104,
116. Improved the DCM performance for the XC3S1200E, Stepping 0 in
104,
91, and
Table
100. Updated block RAM timing in
Table
and
Table
(Table
Table
Table
Table
Table
110. Increased data hold time for Slave Parallel mode to 1.0 ns (T
Table
79). Other minor edits.
92. Added XC3S100E FPGA in CP132 package to
Table
105, and
105, and
96). Removed potentially confusing Note 2 from
Table
79. Clarified Note 2,
87. Updated other I/O timing in
92. Updated pin-to-pin setup and hold timing based on default
99. Updated global clock timing, removed left/right clock buffer limits
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Table 84
83. Expanded description in Note 2,
Table
Table
Table 90
Table
Table
106. Added minimum INIT_B pulse width specification,
106. Corrected links in
to summarize the history of speed file releases after which
Table
86,
97. Updated distributed RAM timing in
and
Table
121.
Revision
Table
Table
Table
82. Improved various timing specifications for
87, and
93. Reduced I/O three-state and set/reset
102. Added DCM parameters for
Table
Table
DC and Switching Characteristics
Table 117
Table
89. Provided input and output
72, providing additional
Table
89. Added
Table
Table
and
77. Updated pin-to-pin
Table
Table
77.
95. Increased T
Table 88
Table
85. Updated
119. Added
Table 98
Table
103,
SMCCD
Table
about
103,
and
85,
) in
AS
159