XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 135

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 94: Test Methods for Timing Measurement at I/Os (Continued)
The capacitive load (C
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
C
are used for all measurements. Any delay that the test fix-
ture might contribute to test measurements is subtracted
from those measurements to produce the final timing num-
bers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V
with the parameters used in
not confuse V
model with V
table. A fourth parameter, C
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
DS312-3 (v3.4) November 9, 2006
Product Specification
Notes:
1.
2.
3.
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
L
value of zero. High-impedance probes (less than 1 pF)
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
Descriptions of the relevant symbols are as follows:
V
V
V
V
V
R
V
The load capacitance (C
According to the PCI specification.
Signal Standard
REF
ICM
M
L
H
T
T
(IOSTANDARD)
– Low-level test voltage at Input pin
– Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required
– Termination voltage
– High-level test voltage at Input pin
– Voltage of measurement point on signal transition
– The common mode input voltage
– The reference voltage for setting the input switching threshold
R
REF
REF
REF
, R
(the input-switching threshold) from the
(the termination voltage) from the IBIS
REF
L
) is connected between the output
, and V
L
) at the Output pin is 0 pF for all signal standards.
Table 94
REF
V
REF
1.25
0.9
1.1
0.9
, is always zero. The four
MEAS
(V)
) correspond directly
(V
T
, R
V
V
V
V
T
REF
REF
REF
REF
, and V
V
Inputs
L
(V)
– 0.5
– 0.5
– 0.5
– 0.5
M
www.xilinx.com
). Do
V
V
V
V
REF
REF
REF
REF
V
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
2. Record the time to V
3. Simulate the same signal standard with the output
4. Record the time to V
5. Compare the results of steps 2 and 4. Add (or subtract)
H
(V)
+ 0.5
+ 0.5
+ 0.5
+ 0.5
driver connected to the test setup shown in
Use parameter values V
C
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including V
and V
load.
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment
yield the worst-case delay of the PCB trace.
REF
is zero.
MEAS
R
values) or capacitive value to represent the
T
50
50
50
50
(Ω)
Outputs
DC and Switching Characteristics
M
MEAS
.
T
, R
.
V
T
1.25
, and V
T
0.9
1.8
0.9
(V)
REF
M
from
, R
(Table
Inputs and
REF
Outputs
Table
Figure
V
V
V
V
V
M
, C
REF
REF
REF
REF
(V)
93) to
REF
94.
73.
,
135