XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 62

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
Quadrant Clock Routing
The clock routing within the FPGA is quadrant-based, as
shown in
total clock signals, labeled ‘A’ through ‘H’ in
Figure
inates either from a global BUFGMUX element along the
top and bottom edges or from a BUFGMUX element along
the associated edge, as shown in
feed the synchronous resource elements (CLBs, IOBs,
block RAM, multipliers, and DCMs) within the quadrant.
62
47. The clock source for an individual clock line orig-
Figure
45. Each clock quadrant supports eight
*(XC3S1200E and
RHCLK input
Double Line
XC3S1600E only)
DCM output*
LHCLK or
Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity
CLK Switch
Figure
Left-/Right-Half BUFGMUX
Matrix
47. The clock lines
Table 41
S
S
I0
I1
I0
I1
www.xilinx.com
0
1
0
1
and
BUFGMUX
O
O
2nd DCM output
1st DCM output
2nd GCLK pin
1st GCLK pin
Double Line
The four quadrants of the device are:
•
•
•
•
Note that the quadrant clock notation (TR, BR, BL, TL) is
separate from that used for similar IOB placement con-
straints.
Top Right (TR)
Bottom Right (BR)
Bottom Left (BL)
Top Left (TL)
Top/Bottom (Global) BUFGMUX
CLK Switch
Matrix
DS312-2 (v3.4) November 9, 2006
S
S
I0
I1
I0
I1
0
1
0
1
DS312-2_16_110706
BUFGMUX
O
O
Product Specification
R