XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 148
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XC3S100E-4CP132GI
Manufacturer Part Number
XC3S100E-4CP132GI
Description
Spartan-3E FPGA Family: Complete Data Sheet
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
1.XC3S100E-4CP132GI.pdf
(231 pages)
- Current page: 148 of 231
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DC and Switching Characteristics
Miscellaneous DCM Timing
Table 109: Miscellaneous DCM Timing
148
Notes:
1.
2.
3.
DCM_RST_PW_MIN
DCM_RST_PW_MAX
DCM_CONFIG_LAG_TIME
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex-4 DCM_RESET specfication.This specification does not apply for Spartan-3E FPGAs.
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.
Symbol
(2)
(3)
Minimum duration of a RST pulse width
Maximum duration of a RST pulse width
Maximum duration from V
configuration successfully completed (DONE pin goes
High) and clocks applied to DCM DLL
www.xilinx.com
Description
CCINT
applied to FPGA
DS312-3 (v3.4) November 9, 2006
Min
N/A
N/A
N/A
N/A
3
Product Specification
Max
N/A
N/A
N/A
N/A
-
seconds
seconds
minutes
minutes
CLKIN
cycles
Units
R
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