XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 155
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XC3S100E-4CP132GI
Manufacturer Part Number
XC3S100E-4CP132GI
Description
Spartan-3E FPGA Family: Complete Data Sheet
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
1.XC3S100E-4CP132GI.pdf
(231 pages)
- Current page: 155 of 231
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Table 118: Configuration Timing Requirements for Attached SPI Serial Flash
DS312-3 (v3.4) November 9, 2006
Product Specification
Notes:
1.
2.
T
T
T
T
f
C
Symbol
CCS
DSU
DH
V
or f
These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
Subtract additional printed circuit board routing delay as required by the application.
R
R
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
Description
www.xilinx.com
T
T
T
V
f
CCS
DSU
DC and Switching Characteristics
C
T
≤
≥
DH
Requirement
T
≤
≤
----------------------------- -
T
MCCLn
T
≤
T
CCLKn min
MCCL1
MCCL1
T
MCCH1
1
–
(
T
–
–
DCC
T
)
T
CCO
CCO
Units
MHz
ns
ns
ns
ns
155
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