XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 162

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Pinout Descriptions
Table 123: Types of Pins on Spartan-3E FPGAs (Continued)
I/Os with Lxxy_# are part of a differential output pair. ‘L’ indi-
cates differential output capability. The “xx” field is a
two-digit integer, unique to each bank that identifies a differ-
ential pin-pair. The ‘y’ field is either ‘P’ for the true signal or
‘N’ for the inverted signal in the differential pair. The ‘#’ field
is the I/O bank number.
Differential Pair Labeling
A pin supports differential standards if the pin is labeled in
the format “Lxxy_#”. The pin name suffix has the following
162
Notes:
1.
Color Code
VCCAUX
CONFIG
VCCINT
VCCO
Type /
# = I/O bank number, an integer between 0 and 3.
JTAG
GND
N.C.
Dedicated configuration pin. Not available as a user-I/O pin. Every package has
two dedicated configuration pins. These pins are powered by VCCAUX. See the
Configuration
Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
Dedicated ground pin. The number of GND pins depends on the package used.
All must be connected.
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on
the package used. All must be connected to +2.5V. See the
Spartan-3E FPGAs
Dedicated internal core logic power supply pin. The number of VCCINT pins
depends on the package used. All must be connected to +1.2V. See the
Powering Spartan-3E FPGAs
this signal.
Along with all the other VCCO pins in the same bank, this pin supplies power to
the output buffers within the I/O bank and sets the input threshold voltage for
some I/O standards. See the
2 for additional information on these signals.
This package pin is not connected in this specific device/package combination
but may be connected in larger devices in the same package.
Spartan-3E
Bank 0
Bank 2
FPGA
section in Module 2 for additional information on these signals.
section in Module 2 for additional information on this signal.
Figure 80: Differential Pair Labeling
Powering Spartan-3E FPGAs
section in Module 2 for additional information on
Description
www.xilinx.com
significance.
a differential input to and a differential output from Bank 1.
"xx" is a two-digit integer, unique for each bank, that
identifies a differential pin-pair.
‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the
inverted. These two pins form one differential pin-pair.
‘#’ is an integer, 0 through 3, indicating the associated
I/O bank.
‘L’ indicates that the pin is part of a differentiaL pair.
IO_L38P_1
IO_L38N_1
IO_L39P_1
IO_L39N_1
Powering
Figure 80
section in Module
provides a specific example showing
Pair Number
Negative Polarity,
Positive Polarity,
DS312-4 (v3.4) November 9, 2006
Inverted Driver
Bank Number
True Driver
DS312-4_00_111105
DONE, PROG_B
TDI, TMS, TCK, TDO
GND
VCCAUX
VCCINT
VCCO_#
N.C.
Pin Name(s) in Type
Product Specification
R