AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 32

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
Figure 3. The Instruction Buffer
Instruction Decode
14
Return Address Stack
32-Kbyte Level-One
Instruction Cache
Address Adders
Branch Target
16 x 16 Bytes
The AMD-K6-2E processor decode logic is designed to decode
multiple x86 instructions per clock (see Figure 4 on page 15).
The decode logic accepts x86 instruction bytes and their
predecode bits from the instruction buffer, locates the actual
instruction boundaries, and generates RISC86 operations from
these x86 instructions.
RISC86 operations are fixed-format internal instructions. Most
RISC86 operations execute in a single clock. RISC86 operations
are combined to perform every function of the x86 instruction
set. Some x86 instructions are decoded into as few as zero
RISC86 opcodes, for instance a NOP, or one RISC86 operation,
decoded into several RISC86 operations.
a register-to-register add. More complex x86 instructions are
Preliminary Information
16 Bytes
Internal Architecture
16 Sets of Predecode Bits
Instruction Buffer
16 Instruction Bytes
Fetch Unit
plus
2:1
16 Bytes
Branch-Target Cache
16 x 16 Bytes
22529B/0—January 2000
Chapter 2