AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 138

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
5.42
Pin Attribute
Pin Location
Summary
Driven and Floated
120
SCYC (Split Cycle)
Output
AL-17
The processor asserts SCYC during misaligned, locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
For purposes of bus cycles, the term aligned means:
SCYC is asserted off the same clock edge as ADS#, and negated
off the clock edge on which NA# or the last expected BRDY# of
the entire locked sequence is sampled asserted. SCYC is only
valid during locked memory cycles.
SCYC is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD.
Any 1-byte transfers
2-byte and 4-byte transfers that lie within 4-byte address
boundaries
8-byte transfers that lie within 8-byte address boundaries
Preliminary Information
Signal Descriptions
22529B/0—January 2000
Chapter 5