AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 123

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
5.24
Pin Attribute
Pin Location
Summary
Driven
5.25
Pin Attribute
Pin Location
Summary
Driven
Chapter 5
HIT# (Inquire Cycle Hit)
HITM# (Inquire Cycle Hit To Modified Line)
Output
AK-06
The processor asserts HIT# during an inquire cycle to indicate
that the cache line is valid within the processor’s instruction or
data cache (also known as a cache hit). The cache line can be in
the modified, exclusive, or shared state.
HIT # is always driven— except in the three-state test mode —
which EADS# is sampled asserted. It is driven in the same state
until the next inquire cycle.
Output
AL-05
The processor asserts HITM # during an inquire cycle to
indicate that the cache line exists in the processor’s data cache
in the modified state. The processor performs a writeback cycle
as a result of this cache hit. If an inquire cycle hits a cache line
that is currently being written back, the processor asserts
HITM # but does not execute another writeback cycle. The
system logic must not expect the processor to assert ADS# each
time HITM# is asserted.
HITM# is always driven—except in the three-state test mode—
cycle the clock edge after the clock edge on which EADS # is
sampled asserted. If HITM # is negated in response to the
inquire address, it remains negated until the next inquire cycle.
If HITM # is asserted in response to the inquire address, it
remains asserted throughout the writeback cycle and is negated
one clock edge after the last BRDY # of the writeback is
sampled asserted.
and only changes state the clock edge after the clock edge on
and, in particular, is driven to represent the result of an inquire
Signal Descriptions
AMD-K6™-2E Processor Data Sheet
105