AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 268

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
13.3
Enter Stop Grant
State
Exit Stop Grant State
250
Stop Grant State
After recognizing the assertion of STPCLK#, the AMD-K6-2E
processor flushes its instruction pipelines, completes all
pending and in-progress bus cycles, and acknowledges the
STPCLK# assertion by executing a Stop Grant special bus cycle.
After BRDY# is sampled asserted during this cycle, and after
EWBE# is also sampled asserted (if not masked off), the
processor enters the Stop Grant state.
The Stop Grant state is like the Halt state in that the processor
disables most of its internal clock distribution in the Stop Grant
state.
In order to support the following operations, the internal PLL
still runs, and some internal resources are still clocked in the
Stop Grant state:
FLUSH# is not recognized in the Stop Grant state (unlike while
in the Halt state).
Upon entering the Stop Grant state, all signals driven by the
processor retain their state as they existed following the
completion of the Stop Grant special cycle.
The AMD-K6-2E processor remains in the Stop Grant state until
it samples STPCLK# negated or RESET asserted. If STPCLK#
is sampled negated, the processor returns to the Normal state in
less than 10 bus clock (CLK) periods. After the transition to the
Norm al state, the processor resumes execution at the
instruction boundary on which STPCLK# was initially
recognized.
If STPCLK# is recognized as negated in the Stop Grant state
and subsequently sampled asserted prior to returning to the
Inquire cycles—The processor transitions to the Stop Grant
Inquire state during an inquire cycle. After returning to the
Stop Grant state following the inquire cycle, the processor
does not execute another Stop Grant special cycle.
Time Stamp Counter (TSC)—The TSC continues to count in
the Stop Grant state.
Signal Sampling—The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
Preliminary Information
Clock Control
22529B/0—January 2000
Chapter 13