AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 117

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
5.18
Pin Attribute
Pin Location
Summary
Driven, Sampled, and
Floated
Chapter 5
D[63:0] (Data Bus)
Bidirectional
See “Pin Designations by Functional Grouping” on page 301.
D[63:0] represent the processor’s 64-bit data bus. Each of the
eight bytes of data that comprise this bus is qualified as valid
by its corresponding byte enable. See “BE[7:0]# (Byte
Enables)” on page 92.
As Outputs: For single-transfer write cycles, the processor drives
D[63:0] with valid data one clock edge after the clock edge on
which ADS# is asserted and D[63:0] remain in the same state
until the clock edge on which BRDY# is sampled asserted. If the
cycle is a writeback—in which case four, 8-byte transfers
occur—D[63:0] are driven one clock edge after the clock edge
on which ADS# is asserted and are subsequently changed off
the clock edge on which each BRDY# assertion of the burst
cycle is sampled.
If the assertion of ADS# represents a pipelined write cycle that
follows a read cycle, the processor does not drive D[63:0] until it
is certain that contention on the data bus will not occur. In this
case, D[63:0] are driven the clock edge after the last expected
BRDY# of the previous cycle is sampled asserted.
As Inputs: During read cycles, the processor samples D[63:0] on
the clock edge on which BRDY# is sampled asserted.
The processor always floats D[63:0] except when they are being
driven during a write cycle as described above. In addition,
D[63:0] are floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts
HLDA in recognition of HOLD.
Signal Descriptions
AMD-K6™-2E Processor Data Sheet
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