AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 194

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
INIT-Initiated
Transition from
Protected Mode to
Real Mode
176
INIT is typically asserted in response to a BIOS interrupt that
writes to an I/O port. This interrupt is often in response to a
Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar
to port 64h in the keyboard controller) that asserts INIT. INIT is
also used to support 80286 software that must return to real
mode after accessing extended memory in protected mode.
The assertion of INIT causes the processor to empty its
pipelines, initialize most of its internal state, and branch to
address FFFF_FFF0h—the same instruction execution starting
point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the Floating-Point state,
the MMX state, Model-Specific Registers (MSRs), the CD and
NW bits of the CR0 register, the time stamp counter, and other
specific internal resources.
Figure 73 on page 177 shows an example in which the operating
system writes to an I/O port, causing the system logic to assert
INIT. The sampling of INIT asserted starts an extended
microcode sequence that terminates with a code fetch from
FFFF_FFF0h, the reset location. INIT is sampled on every clock
edge but is not recognized until the next instruction boundary.
During an I/O write cycle, it must be sampled asserted a
minimum of three clock edges before BRDY# is sampled
asserted if it is to be recognized on the boundary between the
I/O write instruction and the following instruction. If INIT is
asserted synchronously, it can be asserted for a minimum of one
clock. If it is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an assertion
of a minimum of two clocks.
Preliminary Information
Bus Cycles
22529B/0—January 2000
Chapter 6