AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 148

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
5.55
Table 18. Input Pin Types
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
3. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum
4. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and V
5. During a warm reset, while CLK and V
6. When EFER[3] is 1, EWBE# is ignored by the processor.
7. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be
130
Name
A20M#
AHOLD
BF[2:0]
BOFF#
BRDY#
BRDYC#
CLK
EADS#
EWBE#
FLUSH#
HOLD
and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and
must remain asserted at least two clocks.
hold time of two clocks relative to the negation of RESET.
reach specification before it is negated.
prior to its negation.
sampled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which
RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks
relative to the negation of RESET.
3
1
6
2,7
Pin Tables by Type
Type
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock
Synchronous
Synchronous
Asynchronous
Synchronous
CC
are within their specification, RESET must remain asserted for a minimum of 15 clocks
Preliminary Information
Signal Descriptions
Name
IGNNE#
INIT
INTR
INV
KEN#
NA#
NMI
RESET
SMI#
STPCLK#
WB/WT#
2
2
1
2
4,5
1
1
Type
Asynchronous
Asynchronous
Asynchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
22529B/0—January 2000
Chapter 5
CC