AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 182

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
Locked Cycles
Basic Locked
Operation
164
The processor asserts LOCK# during a sequence of bus cycles to
ensure the cycles are completed without allowing other bus
masters to intervene. Locked operations can consist of two to
five cycles. LOCK# is asserted during the following operations:
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s cache are
flushed and invalidated from the cache prior to the locked
operation. If the cache line is in the Modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached. The
processor negates LOCK# for at least one clock between
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
The processor asserts SCYC during misaligned locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
Figure 66 on page 165 shows a pair of read-write bus cycles. It
represents a typical read-modify-write locked operation. The
processor asserts LOCK# off the same clock edge that it asserts
ADS# of the first bus cycle in the locked operation and holds it
asserted until the last expected BRDY# of the last bus cycle in
the locked operation is sampled asserted. (The processor
negates LOCK# off of the same clock edge.)
An interrupt acknowledge sequence
Descriptor Table accesses
Page Directory and Page Table accesses
XCHG instruction
An instruction with an allowable LOCK prefix
Preliminary Information
Bus Cycles
22529B/0—January 2000
Chapter 6