AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 136

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
5.40
Pin Attribute
Pin Location
Summary
Sampled
118
RESET (Reset)
Input
AK-20
When the processor samples RESET asserted, it immediately
flushes and initializes all internal resources and its internal
state including its pipelines and caches, the floating-point
state, the MMX state, the 3DNow! state, and all registers, and
then the processor jumps to address FFFF_FFF0h to start
instruction execution.
The FLUSH# signal is sampled during the falling transition of
RESET to invoke the three-state test mode.
RESET is sampled as a level-sensitive input on every clock
edge. System logic can drive the signal either synchronously or
asynchronously.
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V
reach specification before it is negated.
During a warm reset, while CLK and V
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
Preliminary Information
Signal Descriptions
CC
are within their
22529B/0—January 2000
Chapter 5
CC