AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 226

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
UC/WC Cacheability
Control Register
(UWCCR)
.
Figure 79. UC/WC Cacheability Control Register (UWCCR)—MSR C000_0085h
208
63
Physical Base Address 1
Symbol
UC1
WC1
Description
Uncacheable Memory Type
Write-Combining Memory Type
49
MTRR1
The MTRRs are accessed by addressing the 64-bit MSR known
as the UC/WC Cacheability Control Register (UWCCR). The
MSR address of the UWCCR is C000_0085h. Following reset, all
bits in the UWCCR register are 0. MTRR0 (lower 32 bits of the
UWCCR register) defines the size and memory type of range 0
and MTRR1 (upper 32 bits) defines the size and memory type of
range 1 (see Figure 79 on page 208).
Physical Base Address n (n=0, 1). T h i s a d d re s s i s t h e 1 5 m o s t -
significant bits of the physical base address of the memory
range. The least-significant 17 bits of the base address are not
needed because the base address is by definition always aligned
on a 128-Kbyte boundary.
Physical Address Mask n (n=0, 1). T h i s v a l u e i s t h e 1 5 m o s t -
significant bits of a physical address mask that is used to define
the size of the memory range. This mask is logically ANDed
with both the physical base address field of the UWCCR
register and the physical address generated by the processor. If
the results of the two AND operations are equal, then the
generated physical address is considered within the range.
That is, if:
then, the physical address generated by the processor is in the
range.
Physical Address Mask 1
48
Mask & Physical Base Address = Mask & Physical Address Generated
Preliminary Information
Bits
32
33
Write Merge Buffer
34
W
33
C
1
32
U
C
1
31
Physical Base Address 0
Symbol
UC0
WC0
Description
Uncacheable Memory Type
Write-Combining Memory Type
MTRR0
17
16
Physical Address Mask 0
22529B/0—January 2000
Bits
0
1
2
W
C
0
1
Chapter 9
0
U
C
0