AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 207

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
Table 33. CACHE# Signal Generation
Notes:
1. WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR.
Chapter 8
Cycle Type
Writebacks
Unlocked Reads
Locked Reads
Single Writes
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Table 32 describes how the PCD signal is driven based on the
values of the CD bit of CR0, the PCD bits, and the PG bit of
CR0.
Table 32. PCD Signal Generation
Notes:
1. PCD is taken from PTE or PDE.
Table 33 describes how the CACHE# signal is driven based on
the cycle type, the CI bit of TR12, the PCD signal, and the
UWCCR model-specific register.
CD Bit of CR0
CI Bit of TR12
1
0
0
0
0
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
0
1
Cache Organization
PCD Bit
Don’t care
1
0
1
0
PCD Signal
1
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
0
1
PG Bit of CR0
Don’t care
1
1
0
0
AMD-K6™-2E Processor Data Sheet
WC/UC Range
Access Within
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
PCD Signal
0
1
High
High
Low
Low
Low
1
CACHE#
High
High
High
High
High
Low
Low
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