AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 122

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6™-2E Processor Data Sheet
5.23
Pin Attribute
Pin Location
Summary
Sampled
104
FLUSH# (Cache Flush)
Input
AN-07
In response to sampling FLUSH# asserted, the processor writes
back any data cache lines that are in the modified state,
invalidates all lines in the instruction and data caches, and then
executes a flush acknowledge special cycle. See Table 23 on
page 132 for the bus definition of special cycles.
In addition, FLUSH # is sampled when RESET is negated to
determine if the processor enters the three-state test mode. If
FLUSH # is 0 during the falling transition of RESET, the
proc esso r e nt ers t he t hree- sta te te st mode ins tea d of
performing the normal RESET functions.
FLUSH # is sampled and latched as a falling edge-sensitive
signal. During normal operation (not RESET), FLUSH # is
sampled on every clock edge but is not recognized until the next
instruction boundary. If FLUSH# is asserted synchronously, it
can be asserted for a minimum of one clock. If FLUSH # is
asserted asynchronously, it must have been negated for a
minimum of two clocks, followed by an assertion of a minimum
of two clocks.
FLUSH# is also sampled during the falling transition of RESET.
If RESET and FLUSH# are driven synchronously, FLUSH# is
sampled on the clock edge prior to the clock edge on which
RESET is sampled negated. If RESET is driven asynchronously,
the minimum setup and hold time for FLUSH#, relative to the
negation of RESET, is two clocks.
Preliminary Information
Signal Descriptions
22529B/0—January 2000
Chapter 5