zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 91

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.7.7
CPU Address:h606
Accessed by CPU (R/W)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command. Writing this register will initiate a serial management cycle to the MII management
interface.
13.3.7.8
CPU Address:h607
Accessed by CPU (RO)
13.3.7.9
CPU Address:h608
Accessed by CPU (RO)
13.3.7.10
CPU Address:h609
Accessed by CPU (R/W)
Bits [4:0]
Bit [5]
Bit [6]
Bit [7]
Bits[7:0]:
Bits[5:0]:
Bits[7:6]:
Bits[7:0]:
MIIC3 – MII Command Register 3
MIID0 – MII Data Register 0
MIID1 – MII Data Register 1
USD – One Micro Second Divider
PHY_AD – 5 Bit PHY Address
Reserved
VALID – Data Valid from PHY (Read Only)
RDY – Data is returned from PHY (Read Only)
Divider to get one micro second from M_CLK (only used when not in standard RMII mode)
In a MII or GPSI system, a 50MHz M_CLK may not be available. The system designer can
decide to use another frequency on the M_CLK signal. To compensate for this, this register
is required to be programmed.
For example. If 20MHz is used on M_CLK, to compensate for the difference, this register is
programmed with 20 to provide 1usec for internal reference.
Reserved
MII Data [15:8]
MII Data [7:0]
Zarlink Semiconductor Inc.
ZL50404
91
Data Sheet