zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 86

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.6.28
I²C Address h092+n(Low); CPU Address 570+2n(Low) (n = logical port number)
I²C Address h09A+n(High); CPU Address 571+2n(High)
Accessed by CPU and I²C (R/W)
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define
eight separate ports.
13.3.6.29
I²C Address h0A2, CPU Address 590
Accessed by CPU and I²C (R/W)
The chip allows the CPU to define the priority
13.3.6.30
I²C Address h0A3, CPU Address 591
Accessed by CPU and I²C (R/W)
13.3.6.31
I²C Address h0A4, CPU Address 592
Accessed by CPU and I²C (R/W)
Bits[3:0]:
Bits[7:4]:
Bits[3:0]:
Bits[7:4]:
Bits[3:0]:
Bits[7:4]:
USER_PORT[7:0]_[LOW/HIGH] – User Define Logical Port 0~7
USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
7
7
TCP/UDP Logic Port High
TCP/UDP Logic Port Low
Priority setting, transmission + dropping, for logic port 0
Priority setting, transmission + dropping, for logic port 1 (Default 00)
Priority setting, transmission + dropping, for logic port 2
Priority setting, transmission + dropping, for logic port 3 (Default 00)
Priority setting, transmission + dropping, for logic port 4
Priority setting, transmission + dropping, for logic port 5 (Default 00)
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Data Sheet