zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 67

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.2
13.3.2.1
I²C Address 028; CPU Address:h100
Accessed by CPU and I²C (R/W)
13.3.2.2
I²C Address 029; CPU Address:h101
Accessed by CPU and I²C (R/W)
13.3.2.3
I²C Address 02A, CPU Address:h102
Accessed by CPU and I²C (R/W)
This register indicates the legal egress ports. A “1” on bit 3 means that the packet can be sent to port 3. A “0” on bit
3 means that any packet destined to port 3 will be discarded. This register works with registers 1 to form a 10 bit
mask to all egress ports.
13.3.2.4
I²C Address h34, CPU Address:h103
Accessed by CPU and I²C (R/W)
13.3.2.5
I²C Address h3E, CPU Address:h105
Accessed by CPU and I²C (R/W)
(Group 1 Address) VLAN Group
AVTCL – VLAN Type Code Register Low
AVTCH – VLAN Type Code Register High
PVMAP00_0 – Port 0 Configuration Register 0
PVMAP00_1 – Port 0 Configuration Register 1
PVMAP00_3 – Port 0 Configuration Register 3
Bit [7:0]:
Bit [7:0]:
Bit [3:0]:
Bit[7:4]:
Bit [1:0]:
Bit [7:2]:
Bit [2:0]:
Bit [5:3]:
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0)
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 0x81)
VLAN Mask for port 0 (Default 0xF)
Reserved (Default 0xF)
VLAN Mask for ports 9 to 8 (Default 0x3)
Reserved (Default 0x3F)
Reserved
Default Transmit priority. Used when Bit [7]=1 (Default 0)
Transmit Priority Level 0 (Lowest)
Transmit Priority Level 1
Transmit Priority Level 2
Transmit Priority Level 3 (Highest)
Zarlink Semiconductor Inc.
ZL50404
67
Data Sheet